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1 of 79 GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 GS1560A/gs1561 hd-linx? ii dual-rate deserializer www.gennum.com key features ? smpte 292m and smpt e 259m-c compliant descrambling and nrzi nrz decoding (with bypass) ? dvb-asi 8b/10b decoding ? auto-configuration for hd-sdi and sd-sdi ? serial loop-through cable dr iver output selectable as reclocked or non-recl ocked (GS1560A only) ? dual serial digital input buffers with 2 x 1 mux ? integrated serial digital signal termination ? integrated reclocker ? automatic or manual rate select ion / indication (hd/sd) ? descrambler bypass option ? user selectable additional processing features including: ? crc, trs, anc data checksum, line number and edh crc error detection and correction ? programmable anc data detection ? illegal code remapping ? internal flywheel for noise immune h, v, f extraction ? fifo load pulse ? 20-bit / 10-bit cmos parallel output data bus ? 148.5mhz / 74.25mhz / 27mhz / 13.5mhz parallel digital output ? automatic standards detection and indication ? pb-free and rohs compliant ? 1.8v core power supply and 3.3v charge pump power supply ? 3.3v digital i/o supply ? jtag test interface ? small footprint compatible with gs9060, gs1532, and gs9062 applications ? smpte 292m serial digital interfaces ? smpte 259m-c serial digital interfaces ? dvb-asi serial digital interfaces description the GS1560A/gs1561 is a recloc king deserializer. when used in conjunct ion with the gs1524 automatic cable equalizer and the go1555/go 1525* voltage controlled oscillator, a receive solution can be realized for hd-sd, sd-sdi and dvb-as i applications. in addition to reclocking and deserializing the input data stream, the GS1560A/gs1561 performs nrzi-to-nrz decoding, descramb ling as per smpte 259m-c/292m, and word alignment when operating in smpte mode. when operating in dvb-asi mode, the device will word align the data to k28.5 sync characters and 8b/10b decode the received stream. two serial digital input buffers are provided with a 2x1 multiplexer to allow the device to select from one of two serial digital input signals. the integrated reclocker features a very wide input jitter tolerance of 0.3 ui (total 0.6 ui), a rapid asynchronous lock time, and full compliance with dvb-asi data streams. the GS1560A includes an integr ated cable driver is for serial input loop-through applications. it can be selected to output either buffered or reclocked data. the cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing, and automatic dual slew-rate selection depending on hd/sd operational requirements. the GS1560A/gs1561 also incl udes a range of data processing functions such as error detection and correction, automatic standards detection, and edh support. the device can also detect and extract smpte 352m payload identifier pa ckets and independently identify the received video standard. this information is read from internal registers via the host interface port. line-based crc errors, line number errors, trs errors, edh crc errors and ancillary data checksum errors can all be detected. finally, the device can correct detected errors and insert new trs id words, line-based crc words, an cillary data checksum words, edh crc wo rds, and line numbers. illegal code re-mapping is also available. all processing functions may be individually enabled or disabled via host interface control. the GS1560A/gs1561 is pb-free and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous subcomponents are rohs compliant. *for new designs use go1555
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 2 of 79 functional block diagrams GS1560A functional block diagram gs1561 functional block diagram ddi_1 term 1 term 2 ddi_1 ddi_2 ddi_2 reclocker sdo sdo sdo_en/dis rset s->p smpte de- scramble, word alignment and flywheel h v f dout[19:0] ip_sel carrier_detect rc_byp (o/p mute) pll_lock reset_trst asi_sync_det host interface / jtag test cs_tms sclk_tck sdin_tdi sdout_tdo fifo_ld data_error yanc canc reset jtag/host ioproc_en/dis crc check line number check trs check csum check anc data detection dvb-asi word alignment and 8b/10b decode crc correct line number correct trs correct csum correct edh check & correct illegal code re- map 20bit/10bit i/o buffer & mux fw_en/dis cp_cap dvb_asi pll_lock vco vco lf lb_cont vco_vcc vco_gnd sd/hd master/slave pclk locked lock detect cd1 cd2 smpte_bypass smpte_sync_det rclk_ctrl rclk_bypass ddi_1 term 1 term 2 ddi_1 ddi_2 ddi_2 reclocker s->p smpte de- scramble, word alignment and flywheel h v f dout[19:0] ip_sel carrier_detect reset_trst asi_sync_det host interface / jtag test cs_tms sclk_tck sdin_tdi sdout_tdo fifo_ld data_error yanc canc reset jtag/host ioproc_en/dis crc check line number check trs check csum check anc data detection dvb-asi word alignment and 8b/10b decode crc correct line number correct trs correct csum correct edh check & correct illegal code re- map 20bit/10bit i/o buffer & mux fw_en/dis cp_cap dvb_asi pll_lock vco vco lf lb_cont vco_vcc vco_gnd sd/hd master/slave pclk locked lock detect cd1 cd2 smpte_bypass smpte_sync_det rclk_ctrl
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 3 of 79 revision history contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 functional block diagrams ...................................................................................................... ......................2 1. pin out..................................................................................................................... ..........................................6 1.1 pin assignment GS1560A ..................................................................................................... ..........6 1.2 pin assignment gs1561 ...................................................................................................... ............7 1.3 pin descriptions ........................................................................................................... ......................8 2. electrical characteristics .................................................................................................. ....................... 19 2.1 absolute maximum ratings................................................................................................... ..... 19 2.2 dc electrical characteristics ....... ....................................................................................... ........ 19 2.3 ac electrical characterist ics .............................................................................................. ........ 21 3. input/output circuits ....................................................................................................... ........................ 24 3.1 host interface map......................................................................................................... ................ 26 3.1.1 host interface map (r/w conf igurable registers) ..... ........... .......... ......... ......... ..... 27 3.1.2 host interface map (read only registers) ................................................................ 28 4. detailed description........................................................................................................ .......................... 29 version ecr pcn date changes and / or modifications 12 152053 ? j une 2009 remove d ?proprietary & c onfi d ential? from the footer. 11 150195 50711 j uly 2008 dvb_a s i operation spe c ifi c ation c han g e in master mo d e. 10 143666 42774 j anuary 2007 re c ommen d e d the new g o1555 v c o for new d esi g ns. 9 140423 39452 may 2006 c orre c te d minor typin g errors in fun c tional blo c k dia g ram. mo d ifie d vi d eo format num b ers for system 1125 on ta b le 4-4: s wit c h line position for di g ital s ystems . 8 137405 ? s eptem b er 2005 c onversion to data s heet. a dd e d note on max d evi c e power an d c urrent to ta b le 2-1: d c ele c tri c al c hara c teristi c s . c orre c te d s ol d er reflow profile la b els. 7 136978 ? j une 2005 restore d missin g overlines to pin names. c orre c te d missin g term pin in s erial di g ital input c onne c tion d ia g ram. rephrase d roh s c omplian c e statement. 6 134906 ? april 2005 a dd e d s ol d er reflow profile d es c ription. c larifie d settin g of vd_ s td[4:0], int_pro g an d s td_lo c k b its followin g a reset an d /or removal of input. minor c orre c tion to typi c al appli c ation c ir c uits for b oth parts. a dd e d dvb-a s i pa c ket c ounter information. a dd e d pa c ka g in g data se c tion. c han g e d ? g reen? referen c es to roh s c ompliant.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 4 of 79 4.1 functional overview........................................................................................................ ............. 29 4.2 serial digital input ....................................................................................................... .................. 30 4.2.1 input signal selection ................................................................................................... ... 30 4.2.2 carrier detect input..................................................................................................... ..... 30 4.2.3 single input configuration............................................................................................. 30 4.3 serial digital reclocker ................................................................................................... ............. 31 4.3.1 external vco ............................................................................................................. ......... 31 4.3.2 loop bandwidth........................................................................................................... ...... 31 4.4 serial digital loop-through output (GS1560A only)......................................................... 31 4.4.1 output swing ............................................................................................................. ......... 32 4.4.2 reclocker bypass control ............................................................................................... 33 4.4.3 serial digital output mute.............................................................................................. 3 3 4.5 serial-to-parallel conversion .............................................................................................. ...... 34 4.6 modes of operation ......................................................................................................... ............. 34 4.6.1 lock detect .............................................................................................................. ............ 34 4.6.2 master mode.............................................................................................................. .......... 35 4.6.3 slave mode............................................................................................................... ............ 36 4.7 smpte functionality ........................................................................................................ ............. 36 4.7.1 smpte descrambling and word alignment ............................................................ 37 4.7.2 internal flywheel ........................................................................................................ ...... 37 4.7.3 switch line lock handling............................................................................................. 38 4.7.4 hvf timing signal generation ..................................................................................... 42 4.8 dvb-asi functionality ...................................................................................................... ........... 44 4.8.1 transport packet format................................................................................................. 4 4 4.8.2 dvb-asi 8b/10b decoding and word alignmen t.................................................. 44 4.8.3 status signal outputs .................................................................................................... ... 45 4.9 data through mode .......................................................................................................... ............. 45 4.10 additional processing functions ........................................................................................... .45 4.10.1 fifo load pulse ......................................................................................................... ...... 46 4.10.2 ancillary data detection and indication ................................................................ 47 4.10.3 smpte 352m payload identifier ................................................................................ 51 4.10.4 automatic video standard and data format detection.................................... 51 4.10.5 error detection and indication................................................................................... 55 4.10.6 error correction and insertion ................................................................................... 60 4.10.7 edh flag detection ...................................................................................................... .. 62 4.11 parallel data outputs..................................................................................................... ............. 64 4.11.1 parallel data bus buffers .............................................................................................. 6 4 4.11.2 parallel output in smpte mode..................... ............................................................ 65 4.11.3 parallel output in dvb-asi mode............................................................................. 65 4.11.4 parallel output in data-through mode......... .......................................................... 65 4.11.5 parallel output clock (pclk) ........................ .............................................................. 66 4.12 gspi host interface....................................................................................................... ............... 67 4.12.1 command word descript ion ............... ........... ........... ........... ........... ........... ........... ..... 67 4.12.2 data read and write timing ....................................................................................... 68 4.12.3 configuration and status registers........................................................................... 68
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 5 of 79 4.13 jtag...................................................................................................................... ............................ 69 4.14 device power up........................................................................................................... ............... 70 4.15 device reset.............................................................................................................. ..................... 70 5. application reference design ................................................................................................ ............... 71 5.1 GS1560A typical application circuit (part a).......... ............................................................ 71 5.2 GS1560A typical application circuit (part b) .......... ............................................................ 72 5.3 gs1561 typical application circuit (part a) ......................................................................... 73 5.4 gs1561 typical application circuit (part b).......................................................................... 74 6. references & relevant standards ............................................................................................. ............ 75 7. package & ordering information .............................................................................................. ............ 76 7.1 package dimensions......................................................................................................... ............. 76 7.2 packaging data............................................................................................................. ................... 77 7.3 solder reflow profiles..................................................................................................... .............. 77 7.4 ordering information....................................................................................................... ............. 78
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 6 of 79 1. pin out 1.1 pin assignment GS1560A [ gs15 6 0a core_gnd fw_en/dis canc yanc core_vdd dout19 dout18 dout17 dout1 6 dout15 dout14 dout13 dout12 dout11 dout10 dout9 dout8 dout7 dout 6 dout5 dout4 dout3 dout2 dout1 dout0 io_gnd io_gnd io_vdd io_gnd io_vdd io_vdd pclk rc_byp master/slave locked vco vco vco_gnd vco_vcc lf cp_cap lb_cont cp_gnd 6 1 6 2 6 3 6 4 6 0 6 5 66 6 7 6 8 6 9 70 71 72 73 74 75 7 6 77 78 79 80 cp_vdd pdbuff_gnd pd_vdd buff_vdd cd1 ddi1 term1 ddi1 dvb_asi ip_sel sd/hd 20bit/10bit ioproc_en/dis cd2 ddi2 term2 ddi2 smpte_bypass rset cd_vdd 12345 6 7 8 91011121314151 6 17 18 19 20 59 58 57 5 6 55 54 53 52 51 50 49 48 47 4 6 45 44 43 42 41 core_vdd h v f core_gnd fifo_ld data_error sclk_tck sdin_tdi sdout_tdo cs_tms jtag/host reset_trst sdo sdo cd_gnd sdo_en/dis 21 22 23 24 25 2 6 27 28 29 30 31 32 33 34 35 3 6 37 38 39 40
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 7 of 79 1.2 pin assignment gs1561 gs15 6 1 core_gnd fw_en/dis canc yanc core_vdd dout19 dout18 dout1 dout1 dout1 dout1 dout1 dout1 dout1 dout1 dout9 dout8 dout7 dout 6 dout5 dout4 dout3 dout2 dout1 dout0 io_gnd io_gnd io_vdd io_gnd io_vdd io_vdd pclk master/slave locked vco vco vco_gnd vco_vcc lf cp_cap lb_cont cp_gnd 6 1 6 2 6 3 6 4 6 0 6 5 66 6 7 6 8 6 9 70 71 72 73 74 75 7 6 77 78 79 80 cp_vdd pdbuff_gnd pd_vdd buff_vdd cd1 ddi1 term1 ddi1 dvb_asi ip_sel sd/hd 20bit/10bit ioproc_en/dis cd2 ddi2 term2 ddi2 smpte_bypass rsv 12345 6 7 8 91011121314151 6 17 18 19 20 59 58 57 5 6 55 54 53 52 51 50 49 48 47 4 6 45 44 43 42 41 core_vdd h v f core_gnd fifo_ld data_erro sclk_tck sdin_tdi sdout_tdo cs_tms jtag/host reset_trst 21 22 23 24 25 2 6 27 28 29 30 31 32 33 34 35 3 6 37 38 39 40 nc nc nc nc nc nc
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 8 of 79 1.3 pin descriptions table 1-1: pin descriptions pin number name timing ty p e description 1 c p_vdd ? power power supply c onne c tion for the c har g e pump. c onne c t to +3.3v d c analo g . 2pdbuff_ g nd ? power g roun d c onne c tion for the phase d ete c tor an d serial d i g ital input b uffers. c onne c t to analo g g nd. 3 pd_vdd ? power power supply c onne c tion for the phase d ete c tor. c onne c t to +1.8v d c analo g . 4 buff_vdd ? power power supply c onne c tion for the serial d i g ital input b uffers. c onne c t to +1.8v d c analo g . 5 c d1 non s yn c hronous input s tatu s s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the presen c e of a serial d i g ital input si g nal. normally g enerate d b y a g ennum automati c c a b le equalizer. when low, the serial d i g ital input si g nal re c eive d at the ddi1 an d ddi1 pins is c onsi d ere d vali d . when hi g h, the asso c iate d serial d i g ital input si g nal is c onsi d ere d to b e invali d . in this c ase, the lo c ked si g nal is set low an d all parallel outputs are mute d . 6, 8 ddi1, ddi1 analo g input differential input pair for serial d i g ital input 1. 7 term1 analo g input termination for serial d i g ital input 1. a c c ouple to eq_ g nd. 9dvb_a s inon s yn c hronous input / output c ontrol s i g nal input / s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e an input set b y the appli c ation layer in slave mo d e. this pin an d its fun c tion are not supporte d in master mo d e. s lave mo d e (ma s ter/ s lave = low) when set hi g h in c onjun c tion with s d/hd = hi g h an d s mpte_bypa ss = low, the d evi c e will b e c onfi g ure d to operate in dvb-a s i mo d e. when set low, the d evi c e will not support the d e c o d in g or wor d ali g nment of re c eive d dvb-a s i d ata. 10 ip_ s el non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to sele c t ddi1 / ddi1 or ddi2 / ddi2 as the serial d i g ital input si g nal, an d c d1 or c d2 as the c arrier d ete c t input si g nal. when set hi g h, ddi1 / ddi1 is sele c te d as the serial d i g ital input an d c d1 is sele c te d as the c arrier d ete c t input si g nal. when set low, ddi2 / ddi2 serial d i g ital input an d c d2 c arrier d ete c t input si g nal is sele c te d .
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 9 of 79 11 s d/hd non s yn c hronous input / output c ontrol s i g nal input / s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e an input set b y the appli c ation layer in slave mo d e, an d will b e an output set b y the d evi c e in master mo d e. master mo d e (ma s ter/ s lave = hi g h) the s d/hd si g nal will b e low whenever the re c eive d serial d i g ital si g nal is 1.485 gb /s or 1.485/1.001 gb /s. the s d/hd si g nal will b e hi g h whenever the re c eive d serial d i g ital si g nal is 270m b /s. s lave mo d e (ma s ter/ s lave = low) when set low, the d evi c e will b e c onfi g ure d for the re c eption of 1.485 gb /s or 1.485/1.001 gb /s si g nals only an d will not lo c k to any other serial d i g ital si g nal. when set hi g h, the d evi c e will b e c onfi g ure d for the re c eption of 270m b /s si g nals only an d will not lo c k to any other serial d i g ital si g nal. note: when in slave mo d e, reset the d evi c e after the s d/ hd input has b een initially c onfi g ure d , an d after ea c h su b sequent s d/hd d ata rate c han g e. note: this pin has an internal pull-up resistor of 100k. 12 20 b it/10 b it non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to sele c t the output d ata b us wi d th in s mpte or data-throu g h mo d es. this si g nal is i g nore d in dvb-a s i mo d e. when set hi g h, the parallel output will b e 20- b it d emultiplexe d d ata. when set low, the parallel outputs will b e 10- b it multiplexe d d ata. 13 iopro c _en/di s non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to ena b le or d isa b le i/o pro c essin g features. when set hi g h, the followin g i/o pro c essin g features of the d evi c e are ena b le d : ?edh c r c error c orre c tion ( s d-only) ?an c data c he c ksum c orre c tion ?line- b ase d c r c error c orre c tion (hd-only) ?line num b er error c orre c tion (hd-only) ?tr s error c orre c tion ? ille g al c o d e remappin g to ena b le a su b set of these features, keep iopro c _en/di s hi g h an d d isa b le the in d ivi d ual feature(s) in the iopro c _di s able re g ister a cc essi b le via the host interfa c e. when set low, the i/o pro c essin g features of the d evi c e are d isa b le d , re g ar d less of whether the features are ena b le d in the iopro c _di s able re g ister. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 10 of 79 14 c d2 non s yn c hronous input s tatu s s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the presen c e of a serial d i g ital input si g nal. normally g enerate d b y a g ennum automati c c a b le equalizer. when low, the serial d i g ital input si g nal re c eive d at the ddi2 an d ddi2 pins is c onsi d ere d vali d . when hi g h, the asso c iate d serial d i g ital input si g nal is c onsi d ere d to b e invali d . in this c ase, the lo c ked si g nal is set low an d all parallel outputs are mute d . 15, 17 ddi2, ddi2 analo g input differential input pair for serial d i g ital input 2. 16 term2 analo g input termination for serial d i g ital input 2. a c c ouple to pdbuff_ g nd. 18 s mpte_bypa ss non s yn c hronous input / output c ontrol s i g nal input / s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e an input set b y the appli c ation layer in slave mo d e, an d will b e an output set b y the d evi c e in master mo d e. master mo d e (ma s ter/ s lave = hi g h) the s mpte_bypa ss si g nal will b e hi g h only when the d evi c e has lo c ke d to a s mpte c ompliant d ata stream. it will b e low otherwise. s lave mo d e (ma s ter/ s lave = low) when set hi g h in c onjun c tion with dvb_a s i = low, the d evi c e will b e c onfi g ure d to operate in s mpte mo d e. all i/o pro c essin g features may b e ena b le d in this mo d e. when set low, the d evi c e will not support the d es c ram b lin g , d e c o d in g or wor d ali g nment of re c eive d s mpte d ata. no i/o pro c essin g features will b e availa b le. 19 r s et analo g input gs 1560a use d to set the serial d i g ital loop-throu g h output si g nal amplitu d e. c onne c t to c d_vdd throu g h 281 +/- 1% for 800mv p-p sin g le-en d e d output swin g . n c ?? gs 1561 no c onne c t. 20 c d_vdd ? power gs 1560a power supply c onne c tion for the serial d i g ital c a b le d river. c onne c t to +1.8v d c analo g . n c ?? gs 1561 no c onne c t. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 11 of 79 21 s do_en/di s non s yn c hronous input gs 1560a c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to ena b le or d isa b le the serial d i g ital output loop-throu g h sta g e. when set low, the serial d i g ital output si g nals s do an d s do are d isa b le d an d b e c ome hi g h impe d an c e. when set hi g h, the serial d i g ital output si g nals s do an d s do are ena b le d . n c ?? gs 1561 no c onne c t. 22 c d_ g nd ? power gs 1560a g roun d c onne c tion for the serial d i g ital c a b le d river. c onne c t to analo g g nd. n c ?? gs 1561 no c onne c t. 23, 24 s do, s do analo g output gs 1560a s erial d i g ital loop-throu g h output si g nal operatin g at 1.485 gb /s, 1.485/1.001 gb /s, or 270m b /s. the slew rate of these outputs is automati c ally c ontrolle d to meet s mpte 292m an d 259m spe c ifi c ations a cc or d in g to the settin g of the s d/hd pin. n c ?? gs 1561 no c onne c t. 25 re s et_tr s t non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to reset the internal operatin g c on d itions to d efault settin g s an d to reset the j ta g test sequen c e. host mo d e ( j ta g /ho s t = low) when asserte d low, all fun c tional b lo c ks will b e set to d efault c on d itions an d all input an d output si g nals b e c ome hi g h impe d an c e, in c lu d in g the serial d i g ital outputs s do an d s do. must b e set hi g h for normal d evi c e operation. note: when in slave mo d e, reset the d evi c e after the s d/ hd input has b een initially c onfi g ure d , an d after ea c h su b sequent s d/hd d ata rate c han g e. j ta g test mo d e ( j ta g /ho s t = hi g h) when asserte d low, all fun c tional b lo c ks will b e set to d efault an d the j ta g test sequen c e will b e hel d in reset. when set hi g h, normal operation of the j ta g test sequen c e resumes. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 12 of 79 26 j ta g /ho s t non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to sele c t j ta g test mo d e or host interfa c e mo d e. when set hi g h, cs _tm s , s dout_tdo, s di_tdi an d sc lk_t c k are c onfi g ure d for j ta g b oun d ary s c an testin g . when set low, cs _tm s , s dout_tdo, s di_tdi an d sc lk_t c k are c onfi g ure d as gs pi pins for normal host interfa c e operation. 27 cs _tm ss yn c hronous with sc lk_t c k input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. c hip s ele c t / test mo d e s ele c t host mo d e ( j ta g /ho s t = low) cs _tm s operates as the host interfa c e c hip sele c t, cs , an d is a c tive low. j ta g test mo d e ( j ta g /ho s t = hi g h) cs _tm s operates as the j ta g test mo d e sele c t, tm s , an d is a c tive hi g h. note: if the host interfa c e is not b ein g use d , tie this pin hi g h. 28 s dout_tdo s yn c hronous with sc lk_t c k output c ontrol s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data output / test data output host mo d e ( j ta g /ho s t = low) s dout_tdo operates as the host interfa c e serial output, s dout, use d to rea d status an d c onfi g uration information from the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h) s dout_tdo operates as the j ta g test d ata output, tdo. 29 s din_tdi s yn c hronous with sc lk_t c k input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data in / test data input host mo d e ( j ta g /ho s t = low) s din_tdi operates as the host interfa c e serial input, s din, use d to write a dd ress an d c onfi g uration information to the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h) s din_tdi operates as the j ta g test d ata input, tdi. note: if the host interfa c e is not b ein g use d , tie this pin hi g h. 30 sc lk_t c knon s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data c lo c k / test c lo c k. host mo d e ( j ta g /ho s t = low) sc lk_t c k operates as the host interfa c e b urst c lo c k, sc lk. c omman d an d d ata rea d /write wor d s are c lo c ke d into the d evi c e syn c hronously with this c lo c k. j ta g test mo d e ( j ta g /ho s t = hi g h) sc lk_t c k operates as the j ta g test c lo c k, t c k. note: if the host interfa c e is not b ein g use d , tie this pin hi g h. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 13 of 79 31 data_error s yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. the data_error si g nal will b e low when an error within the re c eive d d ata stream has b een d ete c te d b y the d evi c e. this pin is a lo g i c al 'or'in g of all d ete c ta b le errors liste d in the internal error_ s tatu s re g ister. on c e an error is d ete c te d , data_error will remain low until the start of the next vi d eo frame / fiel d , or until the error_ s tatu s re g ister is rea d via the host interfa c e. the data_error si g nal will b e hi g h when the re c eive d d ata stream has b een d ete c te d without error. note: it is possi b le to pro g ram whi c h error c on d itions are monitore d b y the d evi c e b y settin g appropriate b its of the error_ma s k re g ister hi g h. all error c on d itions are d ete c te d b y d efault. 32 fifo_ld s yn c hronous with p c lk output c ontrol s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. use d as a c ontrol si g nal for external fifo(s). normally hi g h b ut will g o low for one p c lk perio d at s av. 33, 68 c ore_ g nd ? power g roun d c onne c tion for the d i g ital c ore lo g i c . c onne c t to d i g ital g nd. 34 f s yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the odd / even fiel d of the vi d eo si g nal. the f si g nal will b e hi g h for the entire perio d of fiel d 2 as in d i c ate d b y the f b it in the re c eive d tr s si g nals. the f si g nal will b e low for all lines in fiel d 1 an d for all lines in pro g ressive s c an systems. 35 v s yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the portion of the vi d eo fiel d / frame that is use d for verti c al b lankin g . the v si g nal will b e hi g h for the entire verti c al b lankin g perio d as in d i c ate d b y the v b it in the re c eive d tr s si g nals. the v si g nal will b e low for all lines outsi d e of the verti c al b lankin g interval. 36 h s yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the portion of the vi d eo line c ontainin g a c tive vi d eo d ata. h si g nal timin g is c onfi g ura b le via the h_ c onfi g b it of the iopro c _di s able re g ister a cc essi b le via the host interfa c e. a c tive line blankin g (h_ c onfi g = 0 h ) the h si g nal will b e hi g h for the entire horizontal b lankin g perio d , in c lu d in g the eav an d s av tr s wor d s, an d low otherwise. this is the d efault settin g . tr s base d blankin g (h_ c onfi g = 1 h ) the h si g nal will b e hi g h for the entire horizontal b lankin g perio d as in d i c ate d b y the h b it in the re c eive d tr s id wor d s, an d low otherwise. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 14 of 79 37, 64 c ore_vdd ? power power supply c onne c tion for the d i g ital c ore lo g i c . c onne c t to +1.8v d c d i g ital. 38, 39, 42-48, 50 dout[0:9] s yn c hronous with p c lk output parallel data bu s s i g nal levels are lv c mo s /lvttl c ompati b le. dout9 is the m s b an d dout0 is the l s b. hd 20- b it mo d e s d/hd = low 20 b it/10 b it = hi g h c hroma d ata output in s mpte mo d e s mpte_bypa ss =hi g h dvb_a s i = low data output in data-throu g h mo d e s mpte_bypa ss = low dvb_a s i = low hd 10- b it mo d e s d/hd = low 20 b it/10 b it = low for c e d low in all mo d es. s d 20- b it mo d e s d/hd = hi g h 20 b it/10 b it = hi g h c hroma d ata output in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data output in data-throu g h mo d e s mpte_bypa ss = low dvb_a s i = low for c e d low in dvb-a s i mo d e s mpte_bypa ss = low dvb_a s i = hi g h s d 10- b it mo d e s d/hd = hi g h 20 b it/10 b it = low for c e d low in all mo d es. 40, 49, 60 io_ g nd ? power g roun d c onne c tion for d i g ital i/o b uffers. c onne c t to d i g ital g nd. 41, 53, 61 io_vdd ? power power supply c onne c tion for d i g ital i/o b uffers. c onne c t to +3.3v d c d i g ital. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 15 of 79 51, 52, 54-59, 62, 63 dout[19:10] s yn c hronous with p c lk output parallel data bu s s i g nal levels are lv c mo s /lvttl c ompati b le. dout19 is the m s b an d dout10 is the l s b. hd 20- b it mo d e s d/hd = low 20 b it/10 b it = hi g h luma d ata output in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data output in data-throu g h mo d e s mpte_bypa ss = low dvb_a s i = low hd 10- b it mo d e s d/hd = low 20 b it/10 b it = low multiplexe d luma an d c hroma d ata output in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data output in data-throu g h mo d e s mpte_bypa ss = low dvb_a s i = low s d 20- b it mo d e s d/hd = hi g h 20 b it/10 b it = hi g h luma d ata output in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data output in data-throu g h mo d e s mpte_bypa ss = low dvb_a s i = low dvb-a s i d ata in dvb-a s i mo d e s mpte_bypa ss = low dvb_a s i = hi g h s d 10- b it mo d e s d/hd = hi g h 20 b it/10 b it = low multiplexe d luma an d c hroma d ata output in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data input in d ata throu g h mo d e s mpte_bypa ss = low dvb_a s i = low dvb-a s i d ata in dvb-a s i mo d e s mpte_bypa ss = low dvb_a s i = hi g h 65 yan cs yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the presen c e of an c illary d ata in the vi d eo stream. hd mo d e ( s d/hd = low) the yan c si g nal will b e hi g h when the d evi c e has d ete c te d van c or han c d ata in the luma vi d eo stream an d low otherwise. s d mo d e ( s d/hd = low) for 20- b it d emultiplexe d d ata (20 b it/10 b it = hi g h), the yan c si g nal will b e hi g h when van c or han c d ata is d ete c te d in the luma vi d eo stream an d low otherwise. for 10- b it multiplexe d d ata (20 b it/10 b it = low), the yan c si g nal will b e hi g h when van c or han c d ata is d ete c te d anywhere in the d ata stream an d low otherwise. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 16 of 79 66 c an cs yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. use d to in d i c ate the presen c e of an c illary d ata in the vi d eo stream. hd mo d e ( s d/hd = low) the c an c si g nal will b e hi g h when the d evi c e has d ete c te d van c or han c d ata in the c hroma vi d eo stream an d low otherwise. s d mo d e ( s d/hd = low) for 20- b it d emultiplexe d d ata (20 b it/10 b it = hi g h), the c an c si g nal will b e hi g h when van c or han c d ata is d ete c te d in the c hroma vi d eo stream an d low otherwise. for 10- b it multiplexe d d ata (20 b it/10 b it = low), the c an c si g nal will b e hi g h when van c or han c d ata is d ete c te d anywhere in the d ata stream an d low otherwise. 67 fw_en/di s non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to ena b le or d isa b le the noise immune flywheel of the d evi c e. when set hi g h, the internal flywheel is ena b le d . this flywheel is use d in the extra c tion an d g eneration of tr s timin g si g nals, in automati c vi d eo stan d ar d s d ete c tion, an d in manual swit c h line lo c k han d lin g . when set low, the internal flywheel is d isa b le d an d tr s c orre c tion an d insertion is unavaila b le. 69 p c lk ? output parallel data bu s c lo c k s i g nal levels are lv c mo s /lvttl c ompati b le. hd 20- b it mo d ep c lk = 74.25mhz or 74.25/1.001mhz hd 10- b it mo d ep c lk = 148.5mhz or 148.5/1.001mhz s d 20- b it mo d ep c lk = 13.5mhz s d 10- b it mo d ep c lk = 27mhz table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 17 of 79 70 r c _byp non s yn c hronous input /outpu t gs 1560a c ontrol s i g nal input / s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e an input set b y the appli c ation layer in slave mo d e, an d will b e an output set b y the d evi c e in master mo d e. master mo d e (ma s ter/ s lave = hi g h) the r c _byp si g nal will b e hi g h only when the d evi c e has su cc essfully lo c ke d to a s mpte c ompliant input d ata stream. in this c ase, the serial d i g ital loop-throu g h output will b e a re c lo c ke d version of the input. the r c _byp si g nal will b e low whenever the input d oes not c onform to a s mpte c ompliant d ata stream. in this c ase, the serial d i g ital loop-throu g h output will b e a b uffere d version of the input. s lave mo d e (ma s ter/ s lave = low) when set hi g h, the serial d i g ital output will b e a re c lo c ke d version of the input si g nal re g ar d less of whether the d evi c e is in s mpte, dvb-a s i or data-throu g h mo d e. when set low, the serial d i g ital output will b e a b uffere d version of the input si g nal in all mo d es. r s v?? gs 1561 c onne c t to c ore_vdd throu g h 2.2k . 71 ma s ter/ s lave non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to d etermine the input / output sele c tion for the dvb_a s i, s d/hd , r c _byp an d s mpte_bypa ss pins. when set hi g h, the gs 1560a is set to operate in master mo d e where s d/hd , r c _byp ( gs 1560a only) an d s mpte_bypa ss b e c ome status si g nal output pins set b y the d evi c e. in this mo d e, the gs 1560a will automati c ally d ete c t, re c lo c k, d eserialize an d pro c ess s d s mpte an d hd s mpte input d ata. when set low, the gs 1560a is set to operate in slave mo d e where dvb_a s i, s d/hd , r c _byp ( gs 1560a only) an d s mpte_bypa ss b e c ome c ontrol si g nal input pins. in this mo d e, the appli c ation layer must set these external d evi c e pins for the c orre c t re c eption of either s mpte or dvb-a s i d ata. s lave mo d e also supports the re c lo c kin g an d d eserializin g of d ata not c onformin g to s mpte or dvb-a s i streams. 72 lo c ked s yn c hronous with p c lk output s tatu s s i g nal output s i g nal levels are lv c mo s / lvttl c ompati b le. the lo c ked si g nal will b e hi g h whenever the d evi c e has c orre c tly re c eive d an d lo c ke d to s mpte c ompliant d ata in s mpte mo d e or dvb-a s i c ompliant d ata in dvb-a s i mo d e. it will b e low otherwise. 73, 74 v c o, v c o analo g input differential inputs for the external v c o referen c e si g nal. for sin g le en d e d d evi c es su c h as the g o1555/ g o1525*, v c o shoul d b e a c c ouple d to v c o_ g nd. v c o is nominally 1.485 g hz. *for new d esi g ns use g o1555 table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 18 of 79 75 v c o_ g nd ? output power g roun d referen c e for the external volta g e c ontrolle d os c illator. c onne c t to pins 2, 4, 6, an d 8 of the g o1555/ g o1525*. this pin is an output. s houl d b e isolate d from all other g roun d s. *for new d esi g ns use g o1555 76 v c o_v cc ? output power power supply for the external volta g e c ontrolle d os c illator. c onne c t to pin 7 of the g o1555/ g o1525*. this pin is an output. s houl d b e isolate d from all other power supplies. *for new d esi g ns use g o1555 77 lf analo g output c ontrol volta g e to external volta g e c ontrolle d os c illator. nominally +1.25v d c . 78 c p_ c ap analo g input pll lo c k time c onstant c apa c itor c onne c tion. normally c onne c te d to v c o_ g nd throu g h 2.2nf. 79 lb_ c ont analo g input c ontrol volta g e to set the loop b an d wi d th of the inte g rate d re c lo c ker. normally c onne c te d to v c o_ g nd throu g h 40k . 80 c p_ g nd ? power g roun d c onne c tion for the c har g e pump. c onne c t to analo g g nd. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 19 of 79 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value/units s upply volta g e c ore -0.3v to +2.1v s upply volta g e i/o -0.3v to +4.6v input volta g e ran g e (any input) -2.0v to + 5.25v am b ient operatin g temperature -20 c < t a < 85 c s tora g e temperature -40 c < t s t g < 125 c lea d temperature (sol d erin g , 10 se c ) 230 c e s d prote c tion on all pins (see note 2) 1kv note s : 1. see reflow solder profile ( on page 21 ) 2. hbm, per jesda-114b table 2-1: dc electrical characteristics t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol conditions min ty p max units te s t levels notes system operation temperature ran g e t a ?0?70 c ?1 di g ital c ore s upply volta g e c ore_vdd ? 1.65 1.8 1.95 v 1 1 di g ital i/o s upply volta g e io_vdd ? 3.0 3.3 3.6 v 1 1 c har g e pump s upply volta g e c p_vdd ? 3.0 3.3 3.6 v 1 1 phase dete c tor s upply volta g e pd_vdd ? 1.65 1.8 1.95 v 1 1 input buffer s upply volta g e buff_vdd ? 1.65 1.8 1.95 v 1 1 c a b le driver s upply volta g e c d_vdd ? 1.71 1.8 1.89 v 1 1 external v c o s upply volta g e output v c o_v cc ? 2.25 2.50 2.75 v 1 ?
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 20 of 79 +1.8v s upply c urrent gs 1560a i 1v8 ? ? ? 245 ma 1 4 +1.8v s upply c urrent gs 1561 i 1v8 ? ? ? 200 ma 1 ? +3.3v s upply c urrent i 3v3 ???55ma15 total devi c e power gs 1560a p d ? ? ? 625 mw 5 4, 5 total devi c e power gs 1561 p d ? ? ? 545 mw 5 5 digital i/o input lo g i c low v il ??? 0.8v1? input lo g i c hi g hv ih ?2.1??v1? output lo g i c low v ol 8ma ? 0.2 0.4 v 1 ? output lo g i c hi g hv oh 8ma io_vdd - 0.4 ? ? v 1 ? input input bias volta g ev b ? ? 1.45 ? v 6 2 r s et volta g e ( gs 1560a only) v r s et r s et=281 0.54 0.6 0.66 v 1 3 output (GS1560A only) output c ommon mo d e volta g e v c mout 75 loa d , r s et=281 , s d an d hd 0.8 1.0 1.2 v 1 ? te s t level s 1. production test at room temper ature and nominal supply voltage with guardbands for suppl y and temperature ranges. 2. production test at room temper ature and nominal supply voltage with guardbands for supply a nd temperature ranges using correlated test. 3. production test at room te mperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on charac terization of nominal parts. 8. not tested. based on existing de sign/characteriz ation data of similar product. 9. indirect test. note s 1. all dc and ac electrical parame ters within specification. 2. input common mode is set by internal biasing resistors. 3. set by the value of the rset resistor. (GS1560A only) 4. loop-through enabled. (GS1560A only) 5. measured in 20-bit mode. table 2-1: dc electrical characteristics (continued) t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol conditions min ty p max units te s t levels notes
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 21 of 79 2.3 ac electrical characteristics table 2-2: ac electrical characteristics parameter symbol conditions min ty p max units te s t levels notes system s erial di g ital input j itter toleran c e i j t nominal loop b an d wi d th 0.6 ? ? ui 1 1 master mo d e asyn c hronous lo c k time no d ata to hd ? ? 468 us 6,7 2 hd to s d ? ? 260 us 6,7 2 no d ata to s d ? ? 340 us 6,7 2 s d to hd ? ? 256 us 6,7 2 s lave mo d e asyn c hronous lo c k time no d ata to hd ? ? 240 us 6,7 2 no d ata to s d ? ? 197 us 6,7 2 no d ata to dvb-a s i ? ? 68 us 6,7 2 devi c e laten c y 10- b it s d?21?p c lk 6 ? 20- b it hd ? 21 ? p c lk 6 ? dvb-a s i?11?p c lk 6 ? reset pulse wi d th t reset ?1??ms76 serial digital diff erential input s erial input data rate dr ddi ? ? 1.485, 1.485/1.001, 270 ? gb /s gb /s m b /s 1? s erial di g ital input s i g nal s win g v ddi differential with internal 100 input termination 200 600 1000 mv p-p 1? serial digital output (GS1560A only) s erial output data rate dr s do ? ? 1.485, 1.485/1.001, 270 ? gb /s gb /s m b /s 1? s erial output s win g v sdo r s et = 281 loa d = 75 v dd = 1.8v 720 800 880 mvp-p 1 ? s erial output rise time 20% ~ 80% tr s do orl c ompensation usin g re c ommen d e d c ir c uit ? hd si g nal ? 200 260 ps 1 ? orl c ompensation usin g re c ommen d e d c ir c uit ? s d si g nal 400 550 1500 ps 1 ?
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 22 of 79 s erial output fall time 20% ~ 80% tf s do orl c ompensation usin g re c ommen d e d c ir c uit ? hd si g nal ? 235 260 ps 1 ? orl c ompensation usin g re c ommen d e d c ir c uit ? s d si g nal 400 550 1500 ps 1 ? s erial output intrinsi c j itter t i j pseu d oran d om an d patholo g i c al hd si g nal ? 90 125 ps 1 3 pseu d oran d om an d patholo g i c al s d si g nal ? 270 350 ps 1 3 s erial output duty c y c le distortion d c d s do hd (1.485 gb /s) ? 10 ? ps 6,7 4 s d (270m b /s) ? 20 ? ps 6,7 4 parallel output parallel c lo c k frequen c yf p c lk ? 13.5 ? 148.5 mhz 1 ? parallel c lo c k duty c y c le d c p c lk ?405060%1? output data hol d time t oh 20- b it hd 1.0 ? ? ns 1 5 10- b it s d, 50% p c lk duty c y c le 19.5 ? ? ns 1 5 output data delay time t od 20- b it hd ? ? 4.5 ns 1 5 10- b it s d, 50% p c lk duty c y c le ? ? 22.8 ns 1 5 output data rise/fall time tr/tf ? ? ? 1.5 ns 6,7 5 table 2-2: ac electrical characteristics parameter symbol conditions min ty p max units te s t levels notes
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 23 of 79 gspi gs pi input c lo c k frequen c yf sc lk ???6.6mhz1? gs pi input c lo c k duty c y c le d c sc lk ?405060%6,7? gs pi input data s etup time ? ? 0 ? ? ns 6,7 ? gs pi input data hol d time ? ? ? ? 1.43 ns 6,7 ? gs pi output data hol d time ? ? 2.10 ? ? ns 6,7 ? gs pi output data delay time ? ? ? ? 7.27 ns 6,7 ? te s t level s 1. production test at room temper ature and nominal supply voltage with guardbands for suppl y and temperature ranges. 2. production test at room temper ature and nominal supply voltage with guardbands for supply a nd temperature ranges using correlated test. 3. production test at room temper ature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on charac terization of nominal parts. 8. not tested. based on existing de sign/characteriz ation data of similar product. 9. indirect test. note s 1. 6mhz sinewave modulation. 2. hd = 1080i, sd = 525i 3. serial digital output reclocked ( rc_byp = high). 4. serial duty cycle dist ortion is defined here to be the difference between the width of a 1 bit, a nd the width of a 0 bit. (GS1560A only) 5. with 15pf load. (GS1560A only) 6. see device reset on page 70 , figure 4-16 . (GS1560A only) table 2-2: ac electrical characteristics parameter symbol conditions min ty p max units te s t levels notes
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 24 of 79 3. input/output circuits all resistors in ohms, all capacitors in farads, unless otherwise shown. fi g ure 3-1: s erial di g ital input fi g ure 3-2: v c o input fi g ure 3-3: pll loop ban d wi d th c ontrol vdd 50 50 ddi ddi 45k 150k term vdd 25 25 vco vco 1.5k 5k 8 6 5mv 7.2k lb_cont
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 25 of 79 fi g ure 3-4: s erial di g ital output ( gs 1560a only) fi g ure 3-5: v c o c ontrol output & pll lo c k time c apa c itor sdo sdo 300 cp_cap lf
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 26 of 79 3.1 host interface map re g i s ter name addre ss 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 error_ma s k 01ah not use d not use d not use d not use d not use d vd_ s td_ err_ma s k ff_ c r c _ err_ma s k ap_ c r c _ err_ma s k lo c k_err_ ma s k ccs _err_ ma s k y cs _err_ ma s k cc r c _err_ ma s k y c r c _err_ ma s k lnum_err _ma s k s av_err_ ma s k eav_err_ ma s k ff_line_end_f1 019h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ff_line_ s tart_f1 018h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ff_line_end_f0 017h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ff_line_ s tart_f0 016h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_end_f1 015h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_ s tart_f1 014h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_end_f0 013h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_ s tart_f0 012h not use d not use d not use d not use d not use d not use db 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture4 011h not use d not use d not use d not use d not use db 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture3 010h not use d not use d not use d not use d not use db 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture2 00fh not use d not use d not use d not use db 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture1 00eh not use d not use d not use d not use db 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 video_format_out _b 00dh vfo4- b 7vfo4- b 6vfo4- b 5vfo4- b 4vfo4- b 3vfo4- b 2vfo4- b 1vfo4- b 0vfo3- b 7vfo3- b 6vfo3- b 5vfo3- b 4vfo3- b 3vfo3- b 2vfo3- b 1vfo3- b 0 video_format_out _a 00 c hvfo2- b 7vfo2- b 6vfo2- b 5vfo2- b 4vfo2- b 3vfo2- b 2vfo2- b 1vfo2- b 0vfo1- b 7vfo1- b 6vfo1- b 5vfo1- b 4vfo1- b 3vfo1- b 2vfo1- b 1vfo1- b 0 00bh 00ah an c _type5 009h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type4 008h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type3 007h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type2 006h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type1 005h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 video_ s tandard 004h not use d vd s - b 4vd s - b 3vd s - b 2vd s - b 1vd s - b 0int_pro gs td_ lo c k c df- b 3 c df- b 2 c df- b 1 c df- b 0ydf- b 3ydf- b 2ydf- b 1ydf- b 0 edh_fla g 003h not use d an c -ue s an c -ida an c -idh an c -eda an c -edh ff-ue s ff-ida ff-idh ff-eda ff-edh ap-ue s ap-ida ap-idh ap-eda ap-edh 002h error_ s tatu s 001h not use d not use d not use d not use d not use d vd_ s td_ err ff_ c r c _ err ap_ c r c _ err lo c k_err ccs _err y cs _err cc r c _err y c r c _err lnum_err s av_err eav_err iopro c _di s able 000h not use d not use d not use d not use d not use d not use d not use d h_ c onfi g not use d not use d ille g al_ remap edh_ c r c _ in s an c _ cs um _in s c r c _in s lnum_ in s tr s _in s
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 27 of 79 3.1.1 host interface map (r /w configurable registers) re g i s ter name addre ss 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 error_ma s k01ah vd_ s td_ err_ma s k ff_ c r c _ err_ma s k ap_ c r c _ err_ma s k lo c k_err_ ma s k ccs _err_ ma s k y cs _err_ ma s k cc r c _err_ ma s k y c r c _err_ ma s k lnum_err _ma s k s av_err_ ma s k eav_err_ ma s k ff_line_end_f1 019h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ff_line_ s tart_f1 018h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ff_line_end_f0 017h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ff_line_ s tart_f0 016h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_end_f1 015h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_ s tart_f1 014h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_end_f0 013h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ap_line_ s tart_f0 012h b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 011h 010h 00fh 00eh 00dh 00 c h 00bh 00ah an c _type5 009h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type4 008h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type3 007h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type2 006h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 an c _type1 005h b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 004h 003h 002h 001h iopro c _di s able 000h h_ c onfi g ille g al_ remap edh_ c r c _ n s an c _ cs um _in s c r c _in s lnum_ in s tr s _in s
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 28 of 79 3.1.2 host interface map (read only registers) re g i s ter name addre ss 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01ah 019h 018h 017h 016h 015h 014h 013h 012h ra s ter_ s tru c ture4 011h b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture3 010h b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture2 00fh b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ra s ter_ s tru c ture1 00eh b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 video_format_out_ b 00dh vfo4- b 7vfo4- b 6vfo4- b 5vfo4- b 4vfo4- b 3vfo4- b 2vfo4- b 1vfo4- b 0vfo3- b 7vfo3- b 6vfo3- b 5vfo3- b 4vfo3- b 3vfo3- b 2vfo3- b 1vfo3- b 0 video_format_out_ a 00 c hvfo2- b 7vfo2- b 6vfo2- b 5vfo2- b 4vfo2- b 3vfo2- b 2vfo2- b 1vfo2- b 0vfo1- b 7vfo1- b 6vfo1- b 5vfo1- b 4vfo1- b 3vfo1- b 2vfo1- b 1vfo1- b 0 00bh 00ah 009h 008h 007h 006h 005h video_ s tandard 004h vd s - b 4vd s - b 3vd s - b 2vd s - b 1vd s - b 0int_pro gs td_ lo c k c df- b 3 c df- b 2 c df- b 1 c df- b 0ydf- b 3ydf- b 2ydf- b 1ydf- b 0 edh_fla g 003h an c -ue s an c -ida an c -idh an c -eda an c -edh ff-ue s ff-ida ff-idh ff-eda ff-edh ap-ue s ap-ida ap-idh ap-eda ap-edh 002h error_ s tatu s 001h vd_ s td_ err ff_ c r c _ err ap_ c r c _ err lo c k_err ccs _err y cs _err cc r c _err y c r c _err lnum_err s av_err eav_err 000h
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 29 of 79 4. detailed description 4.1 functional overview the GS1560A/gs1561 is a dual-rat e reclocking deserializer. an integrated serial digital loop-through output is also included on the GS1560A only . when used in conjunction with the multi-rate gs1524 adaptive cable equalizer and the external go1555/go1525* voltage controll ed oscillator, a receive solution at 1.485gb/s, 1.485/1.001gb/s or 270mb/s is realized. the device has two basic modes of operatio n which determine precisely how smpte or dvb-asi compliant input data streams are reclocked and processed. in master mode, (master/slave = high), the GS1560A/gs1 561 will automatically detect, reclock, deserializ e and process sd smpte 259m-c or hd smpte 292m input data. in slave mode, (master/slave = low), the application layer must set external device pins for the correct reception of either smpte or dvb-asi data. slave mode also supports the reclocking and deserializing of data not conforming to smpte or dvb-asi streams. the GS1560A includes an integr ated cable driver is for serial input loop-through applications. it can be selected to output either buffered or reclocked data. the cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing, and automatic dual slew-rate selection depending on hd/sd operational requirements. in the digital signal processing core, several data processing functions are implemented including error detection and correction and automatic video standards detection. these features are all enabled by default, but may be individually disabled via internal registers accessible through the gspi host interface. finally, the GS1560A/gs1561 contains a jtag interface for boundary scan test implementations. *for new designs use go1555
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 30 of 79 4.2 serial digital input the GS1560A/gs1561 contains tw o current mode differentia l serial digital input buffers, allowing the device to be connected to two smpt e 259m-c or 292m compliant input signals. both input buffers have internal 50 termination resistors which are connected to ground via the term1 and term2 pins. the input common mode level is set by internal biasing resistors such that the serial digital input signals must be ac coupled into the device. gennum recommends using a capacitor value of 4.7uf to accommodate pathological signals. the input buffers use a separate power supp ly of +1.8v dc supplied via the buff_vdd and pdbuff_gnd pins. 4.2.1 input signal selection a 2x1 input multiplexer is provided to allow the application layer to select between the two serial digital input streams using a single external pin. when ip_sel is set high, serial digital input 1 (ddi1 / ddi1 ) is selected as the in put to the GS1560A/gs1561's reclocker stage. when ip_sel is set low, serial digital input 2 (ddi2 / ddi2 ) is selected. 4.2.2 carrier detect input for each of the differential inputs, an associ ated carrier detect input signal is included, (cd1 and cd2 ). these signals are generated by gennum's family of automatic cable equalizers. when low, cdx indicates that a valid serial digital data stream is being delivered to the GS1560A/gs1561 by the equalizer. when high, the serial di gital input to the device should be considered invalid. if no equalizer precedes the device, the application layer should set cd1 and cd2 accordingly. note: if the gs1524 automatic cabl e equalizer is used, the mute/cd output signal from that device must be translated to tt l levels before passing to the GS1560A/gs1561 cdx inputs. see GS1560A typical application ci rcuit (part a) on page 71 for a recommended transistor network that will set the correct voltage levels. a 2x1 input multiplexer is also provided for these signals. the internal carrier_detect signal is determined by the setting of the ip_sel pin and is used by the lock detect block of the GS1560A/gs1561 to determine th e lock status of the device, (see lock detect on page 34 ). 4.2.3 single inpu t configuration if the application requires a single differential input, the second set of inputs may be left unconnected. tie the associated carrier detect pin high, and leave the termination pin unconnected.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 31 of 79 4.3 serial digital reclocker the output of the 2x1 serial digital inpu t multiplexer passes to the GS1560A/gs1561's internal reclocker stage. the function of this block is to lock to the input data stream, extract a clean clock, and retime the serial digital data to remove high frequency jitter. the reclocker was designed with a 'hexabang' phase and frequency detector. that is, the pfd used can identify six 'degrees' of phase / frequency misalignment between the input data stream and the clock signal provid ed by the vco, and correspondingly signal the charge pump to produce six different control voltages. this results in fast and accurate locking of the pll to the data stream. in master mode, the operating center frequency of the reclocker is toggled between 270mb/s and 1.485gb/s by the lock detect block, (see lock detect on page 34 ). in slave mode, however, the center frequency is determined entirely by the sd/hd input control signal set by the application layer. if lock is achieved, the reclocker provides an internal pll_lock signal to the lock detect block of the device. 4.3.1 external vco the GS1560A/gs1561 requires the external go1555/go1525* voltage controlled oscillator as part of the reclocker's phase-locked loop. this external vco implementation was chosen to ensure high quality reclocking. power for the external vco is generate d entirely by the GS1560A/gs1561 from an integrated voltage regulator. the internal regulator uses +3.3v dc supplied via the cp_vdd / cp_gnd pins to provide +2.5 v dc on the vco_vcc / vco_gnd pins. the control voltage to the vco is output from the GS1560A/gs1561 on the lf pin and requires 4.7k pull-up and pull-down resistors to ensure correct operation. the go1555/go1525* produces a 1. 485ghz reference signal fo r the reclocker, input on the vco pin of the GS1560A/gs1561. both lf an d vco signals should be referenced to the supplied vco_gnd as shown in the recommended application circuit of GS1560A typical application circuit (part a) on page 71 . *for new designs use go1555 4.3.2 loop bandwidth the loop bandwidth of the integrated reclocker is nominally 1.4mhz, but may be increased or decreased via the lb_cont pin. it is recommended that this pin be connected to vco_gnd through 39.2k to maximize the input jitter tolerance of the device. 4.4 serial digital loop-throu gh output (GS1560A only) the GS1560A contains an integrated current mode differential serial digital cable driver with automatic slew rate control. when enabled, this serial digital output provides an active loop-through of the input signal.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 32 of 79 to enable the loop-through output, sdo_en/dis must be set high by the application layer. setting the sdo_en/dis signal low will cause the sdo and sdo output pins to become high impedance, resulting in reduced device power consumption. with suitable external return loss matching circuitry, the GS1560A's loop-through outputs will provide a minimum output return loss of -15db at sd rates. gennum recommends using the gs1528 sdi dual slew-rate cable driver to meet output return loss specifications at hd rates. the integrated cable driver uses a separate power supply of +1.8v dc supplied via the cd_vdd and cd_gnd pins. 4.4.1 output swing nominally, the voltage swing of the seri al digital loop-through output is 800mv p-p single-ended into a 75 load. this is set externally by connecting the rset pin to cd_vdd through 281 . the loop-through output swing may be decreased by increasing the value of the rset resistor. the relationship is appr oximated by the curve shown in figure 4-1 . alternatively, the seri al digital output can drive 800mvp-p into a 50 load. since the output swing is reduced by a factor of approximately one third when the smaller load is used, the rset resistor must be 187 to obtain 800mvp-p. fi g ure 4-1: s erial di g ital loop-throu g h output s win g 300 400 500 6 00 700 800 900 1000 250 300 350 400 450 500 550 6 00 6 50 700 750 rset(w) dv sdo (mv p-p )
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 33 of 79 4.4.2 reclocker bypass control the serial digital loop-through output may be either a buffered version of the serial digital input signal, or a reclocked version of that signal. when operating in slave mode, the application layer may choose the reclocked output by setting rc_byp to logic high. if rc_byp is set low, the data stream will bypass the internal reclocker and the seri al digital output will be a buffered version of the input. when operating in master mode, the device will assert the rc_byp pin high only when it has successfully locked to a smpte input data stream, (see lock detect on page 34 ). in this case, the serial digital loop-through ou tput will be a reclocked version of the input. 4.4.3 serial digital output mute the GS1560A will automatically mu te the serial digital loop -through output in both master and slave modes when the internal carrier_detect signal indicates an invalid serial input. the loop-through output will also be muted in slave mode when sdo/sdo is selected as reclocked, (rc_byp = high), but the lock detect block has failed to lock to the data stream, (locked = low). table 4-1 summarizes the possible states of the serial digital loop-through output data stream. table 4-1: serial digital loop-through output status slave mode sdo cd locked rc_byp (input) re c lo c ked low hi g hhi g h buffered low x low muted low low hi g h muted hi g hlow* x master mode sdo cd locked rc_byp (output) re c lo c ked low hi g hhi g h buffered low low low muted hi g hlow*low *note: lo c ked = hi g h if an d only if c d = low
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 34 of 79 4.5 serial-to-parallel conversion the retimed data and phase-locked clock signals from the reclocker are fed to the serial-to-parallel converter. the function of this block is to extract 10-bit or 20-bit parallel data words from the reclocked serial data stream and present them to the smpte and dvb-asi word alignment blocks simultaneously. 4.6 modes of operation the GS1560A/gs1561 has two basic modes of op eration which determine how the lock detect block controls the integrated reclocker. master mode is enabled when the application layer sets the master/slave pin high, and slave mode is enabled when master/slave is set low. 4.6.1 lock detect the lock detect block controls the center frequency of the integrated reclocker to ensure lock to the received serial digital data stream is achieved, and indicates via the locked output pin that the device has detected the appropriate sync words. in data through mode, the detection for appropriate sync words is turned off. the locked pin is an indication of analog lock. lock detection is a continuous process, which begins at device power up or after a system reset, and continues until the devi ce is powered down or held in reset. the lock detection algorithm first determines if a valid serial digital input signal has been presented to the device by sampling the internal carrier_detect signal. as described in carrier detect input on page 30 , this signal will be low when a good serial digital input signal has been detected. if the carrier_detect signal is high, the serial data into the device is considered invalid, and the vco frequency will be set to the center of the pull range. the locked pin will be low and all outputs of the device except for the pclk output will be muted. instead, the pclk output frequency will operate within +/-3% of the rates shown in table 4-16 of parallel output clock (pclk) on page 66 . note: when the device is operating in dvb- asi slave mode, the parallel outputs will not mute when the carrier_detect signal is high. the locked signal will function normally. if a valid input signal has been detected, an d the device is in master mode, the lock algorithm will enter a hunt phase where four attempts are made to detect the presence of either smpte trs sync words. at each at tempt, the center frequency of the reclocker will be toggled betwee n 270mb/s and 1.485gb/s. assuming that a valid smpte or dvb-asi signal has been applied to the device, asynchronous lock times will be as listed in table 2-2: ac electrical characteristics .
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 35 of 79 in slave mode, the application layer fixes the center frequency of the reclocker such that the lock algorithm will attempt to lock within the single data rate determined by the setting of the sd/hd pin. asynchronous lock times are also listed in the table 2-2: ac electrical characteristics . note: the pclk output will continue to oper ate during the lock detection process. the frequency may toggle between 148mh z and 27mhz when the 20bit/10bit pin is set low, or between 74mhz an d 13.5mhz when 20bit/10bit is set high. for smpte inputs, the lock detect block will only assert the locked output signal high if (1) the reclocker has locked to the input data stream as indicated by the internal pll_lock signal, and (2) trs sync words have been correctly identified. if after four attempts lock has not been achieved, the lock detection algorithm will enter into pll lock mode. in this mode, the reclocker will attempt to lock to the input data stream without detecting smpte trs words. this unassisted process can take up to 10ms to achieve lock. when reclocker lock as indicated by the internal pll_lock signal is ac hieved in this mode, one of the following will occur: 1. in slave mode, data will be passed directly to the parallel outputs without any further processing taking place and the lock ed signal will be asserted high if and only if the smpte_bypass and dvb_asi input pins are set low; or 2. in master mode, the locked signal will be asserted low, the parallel outputs will be latched to logic low, and the smpte_bypass output signal will also be set low. 4.6.2 master mode recall that the GS1560A/gs1561 is said to be in master mode when the master/slave input signal is set high. in this case, the following three device pins become output status signals: ? smpte_bypass ?sd/hd ?rc_byp (GS1560A only) the combined setting of these pins will indicate whether the device has locked to valid smpte data at sd or hd rates. dvb_asi functionality is not supported in master mode. table 4-2 shows the possible combinations.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 36 of 79 4.6.3 slave mode the GS1560A/gs1561 is said to be in slave mode when the master/slave input signal is set low. in this case, the device pins listed in master mode on page 35 , in addition to the dvb_asi pin, become input control signals. it is required that the application layer set th e inputs to reflect the appropriate input data format (smpte_bypass , dvb_asi, and sd/hd ). if just one of these pins is configured incorrectly, the device will not lock to the input data stream, and the data_error pin will be set low. the input signals, rc_byp (GS1560A only), allo ws the application layer to determine whether the serial digital loop-through output will be a reclocked or buffered version of the input, reclocker bypass control on page 33 . table 4-3 shows the required settings for various input formats. 4.7 smpte functionality the GS1560A/gs1561 is said to be in smpte mode once the device has detected smpte trs sync words and locked to the input data stream as described in lock detect on table 4-2: master mode output status signals format pin settings smpte_bypass sd/hd rc_byp (GS1560A only) hd s mpte hi g hlowhi g h s d s mpte hi g hhi g hhi g h not s mpte* low hi g h or low low *note: when the d evi c e lo c ks to the d ata stream in pll lo c k mo d e, the parallel outputs will b e lat c he d low, an d the serial loop-throu g h output ( gs 1560a only) will b e a b uffere d version of the input. table 4-3: slave mode control signals format pin settings smpte_bypass dvb_asi sd/hd hd s mpte hi g hlowlow s d s mpte hi g hlowhi g h dvb-a s ilowhi g hhi g h not s mpte or dvb-a s i* low low hi g h or low *note: s ee data throu g h mo d e on pa g e 45 for a c omplete d es c ription of data throu g h mo d e.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 37 of 79 page 34 . the device will remain in smpte mode until such time that smpte trs sync words fail to be detected. the lock detect block may also drop out of smpte mode under the following conditions: ? reset_trst is asserted low ?cdx is high ? smpte_bypass is asserted low in slave mode ? dvb_asi is asserted high in slave mode trs word detection is a continuous process an d both 8-bit and 10-bit trs words will be identified by the device in both sd and hd modes. in master mode, th e GS1560A/gs1561 sets the smpte_bypass pin high to indicate that it has locked to a smpte input data stream. when operating in slave mode, the application layer must assert the dvb_asi pin low and the smpte_bypass pin high in order to enable smpte operation. 4.7.1 smpte descrambling and word alignment after serial-to-parallel conversion, the internal 10-bit or 20-bit data bus is fed to the smpte descramble and word alignment block. the function of this block is to carry out nrzi-to-nrz decoding, desc rambling accordin g to smpte 259m or 292m, and word alignment of the data to the trs sync words. word alignment occurs when two consecutive valid trs words (sav and eav inclusive) with the same bit alignment have been detected. in normal operation, re-synchronization of the word alignment process will only take place when two consecutive identical trs word positions have been detected. when automatic or manual switch line lock handling is 'actioned', (see switch line lock handling on page 38 ), word alignment re-synchronization will occur on the next received trs code word. 4.7.2 internal flywheel the GS1560A/gs1561 has an intern al flywheel which is used in the generation of internal / external timing signals, in th e detection and correction of certain error conditions and in automatic video standards detection. it is only operational in smpte mode. the flywheel consists of a number of counters and comparators operating at video pixel and video line rates. these counters maintain information about the total line length, active line length, total number of lines per field / frame, and total active lines per field / frame for the received video stream. the flywheel 'learns' the video standard by timing the horizontal and vertical reference information contained in the trs id words of the received video stream. full synchronization of the flywheel to the received video standard therefore requires one complete video frame.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 38 of 79 once synchronization has been achieved, the flywheel will continue to monitor the received trs timing information to maintain synchronization. the fw_en/dis input pin controls the synchronization mechanism of the flywheel. when this input signal is low, the flywheel will re-synchronize all pixel and line based counters on every received trs id word. when fw_en/dis is held high, re-synchronization of the pixel and line based counters will only take place when a consistent synchronization error has been detected. two consecutive video lines with identical trs timing different to the current flywheel timing must occur to initiate re-synchronization of the counters. this provides a measure of noise immunity to internal and external timing signal generation. the flywheel will be disabled should the locked signal or the reset_trst signal be low. a low to high transition on either signal will cause the flywheel to re-acquire synchronization on the next received trs word, regardless of the setting of the fw_en/dis pin. 4.7.3 switch line lock handling the principal of switch line lock handling is that the switching of synchronous video sources will only disturb the horizontal timing and alignment of the stream, whereas the vertical timing remains in synchronization. to account for the horizontal disturbance caused by a synchronous switch, it is necessary to re-synchronize the flywheel immediately after the switch has taken place. rapid re-synchronization of the GS1560A/gs1561 to the ne w video standard can be achieved by controlling the flywheel using the fw_en/dis pin. at every pclk cycle the device samples the fw_en/dis pin. when a logic low to high transition at this pin is detected anywhere within the active line, the flywheel will re-synchronize immediately to the next trs word. this is shown in figure 4-2 . to ensure switch line lock handling, the fw_en/dis signal should be low for a minimum of one pclk cycle (maximum one video line) anywhere within the active portion of the line on which the switch has taken place.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 39 of 79 fi g ure 4-2: s wit c h line lo c kin g the ability to manually re-synchronize the flywheel is also impo rtant when switching asynchronous sources or to implement other non-standardized video switching functions. the GS1560A/gs1561 also implements automatic switch line lo ck handling. by utilizing the synchronous switch poin ts defined by smpte rp168 fo r all major vi deo standards with the automatic video standards detect function, the device automatically re-synchronizes the flywheel at the switch point. this function will occur regardless of the setting of the fw_en/dis pin. eav anc active picture eav anc sav eav anc active picture sav eav anc active picture sav eav anc sav video source 1 eav anc active picture eav anc sav eav anc active picture sav eav anc sav active picture eav anc sav video source 2 eav anc active picture sav eav anc sav data in active picture eav anc sav anc active picture eav anc sav switch point flywheel trs position eav anc active picture sav eav anc sav anc active picture data out active picture eav anc sav eav anc sav fw_en/dis switch video source 1 to 2 flywheel re-synch eav anc active picture eav anc sav eav anc active picture sav eav anc active picture sav eav anc sav video source 1 eav anc active picture eav anc sav eav anc active picture sav eav anc sav active picture eav anc sav video source 2 eav anc active picture sav eav anc sav data in active picture eav anc sav active picture eav anc sav switch point flywheel trs position eav anc active picture sav eav anc sav active picture data out switch video source 2 to 1 eav anc sav active picture eav anc sav flywheel re-synch fw_en/dis
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 40 of 79 the switch line is defined as follows: ? for 525 line interlaced sy stems: re-sync takes place at the end of lines 10 & 273. ? for 525 line progressive systems: re-sync takes place at the end of line 10. ? for 625 line interlaced sy stems: re-sync takes place at the end of lines 6 & 319. ? for 625 line progressive systems: re-sync takes place at the end of line 6. ? for 750 line progressive systems: re-sync takes place at the end of line 7. ? for 1125 line interlaced systems: re-syn c takes place at the end of lines 7 & 568. ? for 1125 line progressive systems: re-sync takes place at the end of line 7. a full list of all major video standards and switching lines is shown in table 4-4 . note 1: the flywheel timing will define the line count such that the line numbers shown in table 4-4 may not correspond directly to the digital line counts. note 2: unless indicated by smpte 352m payload id entifier packets, the GS1560A/gs1561 will not distinguish betwee n 50/60 frames psf and 25/30 frames interlaced for the 1125 line video syst ems; 24 psf will be identified. table 4-4: switch line position for digital systems system video format sampling signal standard parallel interface serial interface switch line no. hd- s dti 1920x1080 (psf) 4:2:2 274m 274m + 348m 292m 7 1920x1080 (2:1) 4:2:2 274m 274m + 348m 292m 7, 569 1280x720 (1:1) 4:2:2 296m 296m + 348m 292m 7 s dti 720x576/50 (2:1) 4:2:2 bt.656 bt.656 + 305m 259m 6, 319 720x483/59.94 (2:1) 4:2:2 125m 125m + 305m 259m 10, 273 750 1280x720/60 (1:1) 4:2:2 296m 296m 296m 7 1280x720/50 (1:1) 4:2:2 296m 296m 296m 7 1280x720/30 (1:1) 4:2:2 296m 296m 296m 7 1280x720/25 (1:1) 4:2:2 296m 296m 296m 7 1280x720/24 (1:1) 4:2:2 296m 296m 296m 7 1125 1920x1080/30 (psf) 4:2:2 274m + rp211 274m + rp211 292m 7 1920x1080/25 (psf) 4:2:2 274m + rp211 274m + rp211 292m 7 1920x1080/24 (psf) 4:2:2 274m + rp211 274m + rp211 292m 7 1920x1080/60 (2:1) 4:2:2 274m + rp211 274m + rp211 292m 7, 569 1920x1080/50 (2:1) 4:2:2 274m + rp211 274m + rp211 292m 7, 569
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 41 of 79 525 960x483/59.94 (2:1) 4:2:2 267m 349m 292m 10, 273 960x483/59.94 (2:1) 4:2:2 267m 267m 259m 10, 273 720x483/59.94 (2:1) 4:4:4:4 267m 349m 292m 10, 273 720x483/59.94 (2:1) 4:4:4:4 267m 347m 344m 10, 273 720x483/59.94 (2:1) 4:4:4:4 267m rp174 344m 10, 273 720x483/59.94 (2:1) 4:4:4:4 267m rp175 rp175 10, 273 720x483/59.94 (2:1) 4:2:2 125m 349m 292m 10, 273 720x483/59.94 (2:1) 4:2:2 125m 125m 259m 10, 273 720x483/59.94 (1:1) 4:2:2 293m 349m 292m 10 720x483/59.94 (1:1) 4:2:2 293m 347m 344m 10 720x483/59.94 (1:1) 4:2:2 293m 293m 294m 10 720x483/59.94 (1:1) 4:2:0 293m 349m 292m 10 720x483/59.94 (1:1) 4:2:0 293m 293m 294m 10 625 720x576/50 (1:1) 4:2:2 bt.1358 349m 292m 6 720x576/50 (1:1) 4:2:2 bt.1358 347m 344m 6 720x576/50 (1:1) 4:2:2 bt.1358 bt.1358 bt.1362 6 720x576/50 (1:1) 4:2:0 bt.1358 349m 292m 6 720x576/50 (1:1) 4:2:0 bt.1358 bt.1358 bt.1362 6 960x576/50 (2:1) 4:2:2 bt.601 349m 292m 6, 319 960x576/50 (2:1) 4:2:2 bt.601 bt.656 259m 6, 319 720x576/50 (2:1) 4:4:4:4 bt.799 349m 292m 6, 319 720x576/50 (2:1) 4:4:4:4 bt.799 347m 344m 6, 319 720x576/50 (2:1) 4:4:4:4 bt.799 bt.799 344m 6, 319 720x576/50 (2:1) 4:4:4:4 bt.799 bt.799 ? 6, 319 720x576/50 (2:1) 4:2:2 bt.601 349m 292m 6, 319 720x576/50 (2:1) 4:2:2 bt.601 125m 259m 6, 319 table 4-4: switch line position for digital systems system video format sampling signal standard parallel interface serial interface switch line no.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 42 of 79 4.7.4 hvf timing signal generation the GS1560A/gs1561 extracts critical timing pa rameters from either the received trs signals (fw_en/dis = low), or from the internal flywheel-timing generator (fw_en/dis = high). horizontal blanking period (h), vertical bl anking period (v), an d even / odd field (f) timing are all extracted and presented to the application layer via the h:v:f status output pins. the h signal timing is configurable via the h_config bit of the internal ioproc_disable register as either active line based blanking, or trs based blanking, (see error correction and insertion on page 60 ). active line based blanking is enabled when the h_config bit is set low. in this mode, the h output is high for the entire horizontal blanking period, including the eav and sav trs words. this is the defaul t h timing used by the device. when h_config is set high, trs based blanking is enabled. in this case, the h output will be high for the entire horizontal blanking period as indicated by the h bit in the received trs id words. the timing of these signals is shown in figure 4-3 .
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 43 of 79 fi g ure 4-3: h, v, f timin g h:v:f timing - hd 20-bit output mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff xyz (eav) 000 000 3ff v f xyz (sav) 000 000 3ff xyz (sav) 000 000 3ff h;v:f timing at sav - hd 10-bit output mode 000 000 3ff 3ff xyz (sav) 000 000 xyz (sav) pclk h v f h:v:f timing at eav - hd 10-bit output mode pclk 000 000 3ff 3ff xyz (eav) 000 000 xyz (eav) multiplexed y/cr/cb data out h v f multiplexed y/cr/cb data out h:v:f timing - sd 20-bit output mode pclk chroma data out luma data out h 000 3ff xyz (eav) 000 v f 000 3ff xyz (sav) 000 h:v:f timing - sd 10-bit output mode multiplexed y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low h_config = high
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 44 of 79 4.8 dvb-asi functionality the gs9060 conforms to dvb-as i standard en 50083-9:1998. the lock detect block may drop out of dvb-asi mode under the following conditions: ? reset_trst is asserted low ?cdx is high ? smpte_bypass is asserted high in slave mode ? dvb_asi is asserted low in slave mode dvb_asi functionality is only supported in slave mode. to operate in dvb_asi mode, the device must be in slave mode, and the application layer must set the sd/hd pin high, in addition to setting smpte_bypass low and dvb_asi high. 4.8.1 transport packet format transport packet structure shall conform to the specifications of en/iso/iec 13818-1 and ets 300 429 for transport stream packets. the packet length can be 188 or 204 bytes. 4.8.2 dvb-asi 8b/10b decoding and word alignment after serial-to-parallel conversion, the internal 10-bit data bus is fed to the dvb-asi 8b/10b decode and word alignment block. the fu nction of this block is to word align the data to the k28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve bit alignment with the data outputs. the extracted 8-bit data will be presented to dout[17:10], bypassing all internal smpte mode data processing. note: when operating in dvb-asi mode, dout[9:0] are forced low.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 45 of 79 4.8.3 status signal outputs in dvb-asi mode, the dout19 and dout18 pins will be configured as dvb-asi status signals syncout and wo rderr respectively. syncout will be high whenever a k28.5 sync character is present on the output. this output may be used to drive the write enable signal of an external fifo, thus providing a means of removing the k28.5 sync characters from the data stream. parallel dvb-asi data may then be clocked out of the fi fo at some rate less than 27mhz. see figure 4-4 . worderr will be high whenever the device has detected a running disparity error or illegal code word. fi g ure 4-4: dvb-a s i fifo implementation usin g the gs 1560a 4.9 data through mode the GS1560A/gs1561 may be configured by the a pplication layer to op erate as a simple serial-to-parallel converter. in this mode, the device presents data to the output data bus without performing any decoding, descrambling or word-alignment. data through mode is enabled only when the master/slave , smpte_bypass , and dvb_asi input pins are set low. under these conditions, the lock detection algorithm enters pll lock mode, (see lock detect on page 34 ), such that the device may reclock data not conforming to smpte or dvb-asi streams. the locked pin will indicated analog lock. when operating in master mode, the GS1560A/gs1561 will set the smpte_bypass signal to logic low if presented with a data stream without smpte trs id words. the locked and data bus outputs will be forced low and the serial digital loop-through output (GS1560A only) will be a buffered version of the input. 4.10 additional pr ocessing functions the GS1560A/gs1561 contains an additional data pr ocessing block which is available in smpte mode only, (see smpte functionality on page 36 ). 8 8 aout ~ hout worderr pclk = 27mhz syncout ddi clk_in clk_out fifo ddi read_clk <27mhz fe ff ts we worderr gs15 6 0a / gs15 6 1
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 46 of 79 4.10.1 fifo load pulse to aid in the application-specific implementation of auto-phasing and line synchronization functions, the GS1560A/gs1561 will generate a fifo load pulse to reset line-based fifo storage. the fifo_ld output pin will normally be high bu t will go low for one pclk period, thereby generating a fifo write reset signal. the fifo load pulse will be generated such th at it is co-timed to the sav xyz code word presented to the output data bus. this ensures that the next pclk cycle will correspond to the first active sample of the video line. figure 4-5 shows the timing relationship between the fifo_ld signal and the output video data. fi g ure 4-5: fifo_ld pulse timin g pclk luma data out chroma data out fifo_ld 3ff 3ff 3ff 3ff 000 000 000 000 xyz (sav) 000 000 000 000 xyz (sav) xyz (sav) xyz (sav) multiplexed y/cr/cb data out pclk fifo_ld fifo load pulse - hd 10bit output mode fifo load pulse - hd 20bit output mode 3ff 3ff 000 000 000 000 xyz (sav) multiplexed y/cr/cb data out pclk pclk luma data out chroma data out fifo_ld fifo_ld xyz (sav) fifo load pulse - sd 10bit output mode fifo load pulse - sd 20bit output mode
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 47 of 79 4.10.2 ancillary data detection and indication the GS1560A/gs1561 will dete ct all types of ancillary data in either the vertical or horizontal blanking spaces and indicate vi a the status signal output pins yanc and canc the position of ancillary data in the output data stream. these status signal outputs are synchronous with pclk and can be used as clock enables to external logic, or as write enables to an extern al fifo or othe r memory device. when operating in hd mode, (sd/hd = low), the yanc signal will be high whenever ancillary data is detected in the luma data stream, and the canc signal will be high whenever ancillary data is detected in the chroma data stream. in sd mode, (sd/hd = high), the yanc and canc signal operation will depend on the output data format. for 20-bit demultiplexed data, (see parallel data outputs on page 64 ), the yanc and canc signals will oper ate independently. however, for 10-bit multiplexed data, the yanc and canc signal s will both be high whenever ancillary data is detected. the signals will be high from the start of the ancillary data preamble and will remain high until after the an cillary data checksum. the operation of the yanc and canc signals is shown in figure 4-6 .
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 48 of 79 fi g ure 4-6: yan c an d c an c output s i g nal timin g anc data detection - hd 20bit output mode anc data detection - hd 10bit output mode 000 000 000 000 3ff 3ff 3ff 3ff 3ff 3ff 3ff 3ff did ydid did dbn dbn anc data anc data anc data anc data dc dc blank blank csum csum canc ycsum ccsum yanc canc pclk luma data out chroma data out multiplexed y/cr/cb data out yanc canc pclk blank did dbn anc data anc data anc data anc data anc data anc data anc data anc data blank csum csum 3ff 000 000 did 3ff dbn dc 3ff 3ff dc anc data anc data detection - sd 20bit output mode anc data detection - sd 10bit output mode pclk multiplexed y/cr/cb data out yanc/canc pclk luma data out chroma data out yanc canc
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 49 of 79 4.10.2.1 programmable ancillary data detection although the GS1560A/gs1561 will detect all ty pes of ancillary data by default, it also allows the host interface to specifically program up to five different ancillary data types for detection. this is accomplish ed via the anc_type register ( table 4-5 ). for each data type to be detected, the host interface must program the did and/or sdid of the ancillary data type of interest. the GS1560A/gs1561 will compare the received did and/or sdid with the programmed values and assert yanc and canc only if an exact match is found. if any did or sdid value is set to zero in the anc_type register, no comparison or match will be made for that value. for example, if the did is programmed but the sdid is set to zero, the device will detect all ancillary data types matching the did value, regardless of the sdid. in the case where all five did and sdid values are set to ze ro, the GS1560A/gs1561 will detect all ancillary data types. this is the default setting after device reset. where one or more, but less than five, did and/or sdid values have been programmed, then only those matching ancillary data types will be detected and indicated. note 1: the GS1560A/gs1561 will always dete ct edh ancillary da ta packets for edh error detection purposes, regardless of wh ich did/sdid values have been programmed for ancillary data indication, (see edh crc error detection on page 57 ). note 2: see smpte 291m for a defi nition of ancillary data terms.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 50 of 79 table 4-5: host interface description for programmable ancillary data type registers register name bit name description r/w default an c _type1 a dd ress: 005h 15-8 an c _type1[15:8] use d to pro g ram the did for an c illary d ata d ete c tion at the yan c an d c an c output r/w 0 7-0 an c _type1[7:0] use d to pro g ram the s did for an c illary d ata d ete c tion at the yan c an d c an c output. s houl d b e set to zero if no s did is present in the an c illary d ata pa c ket to b e d ete c te d . r/w 0 an c _type2 a dd ress: 006h 15-8 an c _type2[15:8] use d to pro g ram the did for an c illary d ata d ete c tion at the yan c an d c an c output r/w 0 7-0 an c _type2[7:0] use d to pro g ram the s did for an c illary d ata d ete c tion at the yan c an d c an c output. s houl d b e set to zero if no s did is present in the an c illary d ata pa c ket to b e d ete c te d . r/w 0 an c _type3 a dd ress: 007h 15-8 an c _type3[15:8] use d to pro g ram the did for an c illary d ata d ete c tion at the yan c an d c an c output r/w 0 7-0 an c _type3[7:0] use d to pro g ram the s did for an c illary d ata d ete c tion at the yan c an d c an c output. s houl d b e set to zero if no s did is present in the an c illary d ata pa c ket to b e d ete c te d . r/w 0 an c _type4 a dd ress: 008h 15-8 an c _type4[15:8] use d to pro g ram the did for an c illary d ata d ete c tion at the yan c an d c an c output r/w 0 7-0 an c _type4[7:0] use d to pro g ram the s did for an c illary d ata d ete c tion at the yan c an d c an c output. s houl d b e set to zero if no s did is present in the an c illary d ata pa c ket to b e d ete c te d . r/w 0 an c _type5 a dd ress: 009h 15-8 an c _type5[15:8] use d to pro g ram the did for an c illary d ata d ete c tion at the yan c an d c an c output r/w 0 7-0 an c _type5[7:0] use d to pro g ram the s did for an c illary d ata d ete c tion at the yan c an d c an c output. s houl d b e set to zero if no s did is present in the an c illary d ata pa c ket to b e d ete c te d . r/w 0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 51 of 79 4.10.3 smpte 352m payload identifier the GS1560A/gs1561 can receive and detect the presence of the smpte 352m payload identifier ancillary data packet. this four word payload identifier packet may be used to indicate the transport mechanism, frame rate and line scanning / sampling structure. upon reception of this packet, the device will extract the four words describing the video format being transported and make this information available to the host interface via the four video_format_out registers ( table 4-6 ). the video_format_out registers will only be updated if the received checksum is the same as the locally calculated checksum. these registers will be cleared to zero, indicating an undefined format, if the device loses lock to the input data stream (locked = low), or if the smpte_bypass pin is asserted low. this is also the default setting after device reset. the smpte 352m packet should be received once per field for interl aced systems and once per frame for progressive systems. if the packet is not received for two complete video frames, the video_format_out registers will be cleared to zero. 4.10.4 automatic video standard and data format detection the GS1560A/gs1561 can independ ently detect the input vi deo standard and data format by using the timing parameters extracted from the received trs id words. this information is presented to the host interface via the video_standard register ( table 4-7 ). total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and presented to the host interface via the raster_structure registers ( table 4-8 ). these line and sample count registers are updated once per frame at the end of line 12. this is in addition to the information contained in the video_standard register. after device reset, the four raster_ structure registers default to zero. table 4-6: host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_out_b a dd ress: 00dh 15-8 s mpte352m byte 4 data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 s mpte352m byte 3 data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_out_a a dd ress: 00 c h 15-8 s mpte352m byte 2 data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 s mpte352m byte 1 data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 52 of 79 4.10.4.1 video standard indication the video standard codes reported in the vd_std[4:0] bits of the video_standard register represent the smpte standards as shown in table 4-9 . in addition to the 5-bit video standard code word, the video_standard register also contains two status bits. the std_lock bit will be set high whenever the flywheel has achieved full synchronization. the int_prog bit will be set low if the detected video standard is progressive and high if the detected video standard is interlaced. the vd_std[4:0], std_lock and int_prog bits of the video_standard register will default to zero after device reset. the vd_std[4:0] and int_prog bits will also default to zero if the device loses lock to the input data stream, (locked = low), or if the smpte_bypass pin is asserted low. the std_loc k bit will retain its previous value if the input is removed. table 4-7: host interface description for video standard and data format register register name bit name description r/w default video_ s tandard a dd ress: 004h 15 ? not use d . ?? 14-10 vd_ s td[4:0] vi d eo data s tan d ar d (see ta b le 4-9 ). r 0 9int_pro g interla c e/pro g ressive: s et low if d ete c te d vi d eo stan d ar d is pro g re ss ive an d is set hi g h if it is interla c ed. r0 8 s td_lo c k s tan d ar d lo c k: s et hi g h when flywheel has a c hieve d full syn c hronization. r0 7-4 c data_format[3:0] c hroma data format. s et hi g h in s d mo d e. in d i c ates c hroma d ata format in hd mo d e (see ta b le 4-10 ). rf h 3-0 ydata_format[3:0] luma data format. in d i c ates luma d ata format in hd mo d e an d d ata format in s d mo d e (see ta b le 4-10 ). rf h table 4-8: host interface descript ion for raster structure registers register name bit name description r/w default ra s ter_ s tru c ture1 a dd ress: 00eh 15-12 ? not use d .?? 11-0 ra s ter_ s tru c ture1[11:0] wor d s per a c tive line. r 0 ra s ter_ s tru c ture2 a dd ress: 00fh 15-12 ? not use d .?? 11-0 ra s ter_ s tru c ture2[11:0] wor d s per total line. r 0 ra s ter_ s tru c ture3 a dd ress: 010h 15-11 ? not use d .?? 10-0 ra s ter_ s tru c ture3[10:0] total lines per frame. r 0 ra s ter_ s tru c ture4 a dd ress: 011h 15-11 ? not use d .?? 10-0 ra s ter_ s tru c ture4[10:0] a c tive lines per fiel d .r0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 53 of 79 table 4-9: supported video standards vd_std[4:0] smpte standard video format length of hanc length of active video to t a l samples smpte352m lines 00h 296m (hd) 1280x720/60 (1:1) 358 1280 1650 13 01h 296m (hd) 1280x720/60 (1:1) - em 198 1440 1650 13 02h 296m (hd) 1280x720/30 (1:1) 2008 1280 3300 13 03h 296m (hd) 1280x720/30 (1:1) - em 408 2880 3300 13 04h 296m (hd) 1280x720/50 (1:1) 688 1280 1980 13 05h 296m (hd) 1280x720/50 (1:1) - em 240 1728 1980 13 06h 296m (hd) 1280x720/25 (1:1) 2668 1280 3960 13 07h 296m (hd) 1280x720/25 (1:1) - em 492 3456 3960 13 08h 296m (hd) 1280x720/24 (1:1) 2833 1280 4125 13 09h 296m (hd) 1280x720/24 (1:1) - em 513 3600 4125 13 0ah 274m (hd) 1920x1080/60 (2:1) or 1920x1080/30 (psf) 268 1920 2200 10, 572 0bh 274m (hd) 1920x1080/30 (1:1) 268 1920 2200 18 0 c h 274m (hd) 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2640 10, 572 0dh 274m (hd) 1920x1080/25 (1:1) 708 1920 2640 18 0eh 274m (hd) 1920x1080/25 (1:1) - em 324 2304 2640 18 0fh 274m (hd) 1920x1080/25 (psf) - em 324 2304 2640 10, 572 10h 274m (hd) 1920x1080/24 (1:1) 818 1920 2750 18 11h 274m (hd) 1920x1080/24 (psf) 818 1920 2750 10, 572 12h 274m (hd) 1920x1080/24 (1:1) - em 338 2400 2750 18 13h 274m (hd) 1920x1080/24 (psf) - em 338 2400 2750 10, 572 14h 295m (hd) 1920x1080/50 (2:1) 444 1920 2376 10, 572 15h 260m (hd) 1920x1035/60 (2:1) 268 1920 2200 10, 572 16h 125m ( s d) 1440x487/60 (2:1) (or d ual link pro g ressive) 268 1440 1716 13, 276 17h 125m ( s d) 1440x507/60 (2:1) 268 1440 1716 13, 276 19h 125m ( s d) 525-line 487 g eneri c ? ? 1716 13, 276 1bh 125m ( s d) 525-line 507 g eneri c ? ? 1716 13, 276
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 54 of 79 4.10.4.2 data format indication the luma and chroma data format codes wi ll be reported in the ydata_format[3:0] and cdata_format[3:0] bits of the video_ standard register when the device is operating in hd mode, (sd/hd = low). in sd or dvb-asi mode, the data fo rmat code will only appear in the ydata_format[3:0] bits. the cdata_fo rmat[3:0] bits will be set to 'f h '. these codes represent the data formats listed in table 4-10 . the ydata_format[3:0] and cdata_form at[3:0] bits of the video_standard register will default to 'f h ' after device reset. these bits will also default to 'f h ' if the device loses lock to the input data stream, (locked = low), or if data-through mode is enabled, (see data through mode on page 45 ). 18h itu-r bt.656 ( s d) 1440x576/50 (2:1) (or d ual link pro g ressive) 280 1440 1728 9, 322 1ah itu-r bt.656 ( s d) 625-line g eneri c (em) ? ? 1728 9, 322 1dh unknown hd ? ? ? ? ? 1eh unknown s d? ? ? ? ? 1 c h, 1fh reserve d ????? table 4-9: supported video standards (continued) vd_std[4:0] smpte standard video format length of hanc length of active video to t a l samples smpte352m lines table 4-10: data format codes ydata_format[3:0] or cdata_format[3:0] data format applicable standards 0h s dti dv c pro - no e cc s mpte 321m 1h s dti dv c pro - e cc s mpte 321m 2h s dti dv c am s mpte 322m 3h s dti c p s mpte 326m 4h other s dti fixe d b lo c k size ? 5h other s dti varia b le b lo c k size ? 6h s di ? 7h dvb-a s i? 8h tdm d ata s mpte 346m 9h ~ eh reserve d ? fh unknown d ata format ?
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 55 of 79 4.10.5 error detect ion and indication the GS1560A/gs1561 contains a number of error detection func tions to enhance operation of the device when operating in smpte mode. these functions, (except lock error detection), will not be available in either dvb-asi or data-through operating modes. see dvb-asi functionality on page 44 and data through mode on page 45 . the device maintains an error status register at address 001 h called error_status ( table 4-11 ). each type of error has a specific flag or bit in this register which is set high whenever that error is detected. the error_status register will be cleared at th e start of each video field or when read by the host interface, which ever condition occurs first. all bits of the error_status register except the lock_err bit will also be cleared if a change in the video standard is detected, or under the following conditions: ? reset_trst is held low ? locked is asserted low ? smpte_bypass is asserted low in slave mode in addition to the error_status regi ster, a register called error_mask ( table 4-12 ) is included which allows the host interface to select the specific error conditions that will be detected. there is one bit in the error_mask register for each type of error represented in the error_status register. the bits of the error_mask register will default to '0' after device reset, thus enabling all error types to be detected. the host interface may disable individual error detection by setting the corresponding bit high in this register. error conditions are also indicated to the application layer via the status signal pin data_error . this output pin is a logical 'or'ing of each error status flag stored in the error_status register. data_error is normally high, but will be set low by the device when an error condition that has not been masked is detected.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 56 of 79 table 4-11: host interface description for error status register register name bit name description r/w default error_ s tatu s a dd ress: 001h 15-11 ? not use d . ?? 10 vd_ s td_err vi d eo s tan d ar d error fla g . s et hi g h when a mismat c h b etween the re c eive d s mpte352m pa c kets an d the c al c ulate d vi d eo stan d ar d o cc urs. r0 9ff_ c r c _err full fiel d c r c error fla g . s et hi g h in s d mo d e when a full fiel d (ff) c r c mismat c h has b een d ete c te d in fiel d 1 or 2. r0 8ap_ c r c _err a c tive pi c ture c r c error fla g . s et hi g h in s d mo d e when an a c tive pi c ture (ap) c r c mismat c h has b een d ete c te d in fiel d 1 or 2. r0 7lo c k_err lo c k error fla g . s et hi g h whenever the lo c k pin is low (in d i c atin g the d evi c e not c orre c tly lo c ke d ). r0 6 ccs _err c hroma c he c ksum error fla g . s et hi g h when an c illary d ata pa c ket c he c ksum error has b een d ete c te d in the c c hannel. r0 5y cs _err luma c he c ksum error fla g . s et hi g h when an c illary d ata pa c ket c he c ksum error has b een d ete c te d in the y c hannel. r0 4 cc r c _err c hroma c r c error fla g . s et hi g h in hd mo d e when a mismat c h o cc urs b etween the c al c ulate d an d re c eive d c r c values in the c c hannel. r0 3y c r c _err luma c r c error fla g . s et hi g h in hd mo d e when a mismat c h o cc urs b etween the c al c ulate d an d re c eive d c r c values in the y c hannel. r0 2 lnum_err line num b er error fla g . s et hi g h in hd mo d e when a mismat c h o cc urs b etween the c al c ulate d an d re c eive d line num b ers. r0 1 s av_err s tart of a c tive vi d eo error fla g . s et hi g h when tr s errors are d ete c te d in either 8- b it or 10- b it tr s wor d s. in hd mo d e only y c hannel tr s c o d es will b e c he c ke d . fw_en/di s must b e set hi g h. r0 0eav_err en d of a c tive vi d eo error fla g . s et hi g h when tr s errors are d ete c te d in either 8- b it or 10- b it tr s wor d s. in hd mo d e only y c hannel tr s c o d es will b e c he c ke d . fw_en/di s must b e set hi g h. r0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 57 of 79 4.10.5.1 video standard error detection if a mismatch between the received smpte 352m packets and the calculated video standard occurs, the GS1560A/gs1561 will indica te a video standard error by setting the vd_std_err bit of the error_status register high. 4.10.5.2 edh crc error detection the GS1560A/gs1561 calculates full field (ff) and active pictur e (ap) crc words according to smpte rp 165 in support of error detectio n and handling packets in sd signals. these calculated crc values are compared with the received crc values. if a mismatch is detected, the error is flagged in the ap _crc_err and/or ff_crc_err bits of the error_status register. these two flags are shared between fields 1 and 2. the ap_crc_err bit will be set high when an active picture crc mismatch has been detected in field 1 or 2. the ff_crc_err bit will be set high wh en a full field crc mismatch has been detected in field 1 or 2. edh crc errors will only be indicated when the device is operating in sd mode (sd/hd = high), and when the device has correctly received edh packets. smpte rp165 specifies the calculation ranges and scope of edh da ta for standard 525 and 625 component digital interfaces. the gs 1560a/gs1561 will utilize these standard ranges by default. if the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the edh calc ulation ranges will be employed: table 4-12: host interface descr iption for error mask register register name bit name description r/w default error_ma s k a dd ress: 01ah 15-11 ? not use d .?? 10 vd_ s td_err_ma s kvi d eo s tan d ar d error fla g mask b it. r/w 0 9ff_ c r c _err_ma s k full fiel d c r c error fla g mask b it. r/w 0 8ap_ c r c _err_ma s ka c tive pi c ture c r c error fla g mask b it. r/w 0 7lo c k_err_ma s klo c k error fla g mask b it. r/w 0 6 ccs _err_ma s k c hroma c he c ksum error fla g mask b it. r/w 0 5y cs _err_ma s kluma c he c ksum error fla g mask b it. r/w 0 4 cc r c _err_ma s k c hroma c r c error fla g mask b it. r/w 0 3y c r c _err_ma s kluma c r c error fla g mask b it. r/w 0 2 lnum_err_ma s kline num b er error fla g mask b it. r/w 0 1 s av_err_ma s k s tart of a c tive vi d eo error fla g mask b it. r/w 0 0eav_err_ma s ken d of a c tive vi d eo error fla g mask b it. r/w 0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 58 of 79 1. ranges will be based on the line and pixel ranges programmed by the host interface; or 2. in the absence of user-programmed calculation ranges, ranges will be determined from the received trs timing information. the registers available to the host interf ace for programming edh calculation ranges include active picture and full field line start and end positions for both fields. table 4-13 shows the relevant registers, which default to '0' after device reset. if any or all of these register values are zero, then the edh crc calculation ranges will be determined from the flywheel generated h signal. the first active and full field pixel will always be the first pixel after the sav trs code word. the last active and full field pixel will always be the last pixel befo re the start of the eav trs code words. table 4-13: host interface description for edh calculation range registers register name bit name description r/w default ap_line_ s tart_f0 a dd ress: 012h 15-10 ? not use d .?? 9-0 ap_line_ s tart_f0[9:0] fiel d 0 a c tive pi c ture start line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 ap_line_end_f0 a dd ress: 013h 15-10 ? not use d .?? 9-0 ap_line_end_f0[9:0] fiel d 0 a c tive pi c ture en d line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 ap_line_ s tart_f1 a dd ress: 014h 15-10 ? not use d .?? 9-0 ap_line_ s tart_f1[9:0] fiel d 1 a c tive pi c ture en d line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 ap_line_end_f1 a dd ress: 015h 15-10 ? not use d .?? 9-0 ap_line_end_f1[9:0] fiel d 1 a c tive pi c ture en d line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 ff_line_ s tart_f0 a dd ress: 016h 15-10 ? not use d .?? 9-0 ff_line_ s tart_f0[9:0] fiel d 0 full fiel d start line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 ff_line_end_f0 a dd ress: 017h 15-10 ? not use d .?? 9-0 ff_line_end_f0[9:0] fiel d 0 full fiel d start line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 ff_line_ s tart_f1 a dd ress: 018h 15-10 ? not use d .?? 9-0 ff_line_ s tart_f1[9:0] fiel d 1 full fiel d start line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 59 of 79 4.10.5.3 lock error detection the locked pin of the GS1560A/gs1561 indica tes the lock st atus of the reclocker and lock detect blocks of the device. only when the locked pin is asserted high has the device correctly locked to the received data stream, (see lock detect on page 34 ). the GS1560A/gs1561 will also indi cate lock error to the ho st interface when locked = low by setting the lock_err bit in the error_status register high. 4.10.5.4 ancillary data checksum error detection the GS1560A/gs1561 will calculate checksums for all received an cillary data and compare the calculated values to the received checksum words. if a mismatch is detected, the error is flagged in the ccs_err and/or ycs_err bits of the error_status register. when operating in hd mode, (sd/hd = low), the device will make comparisons on both the y and c channels separately. if an error condition in the y channel is detected, the ycs_err bit will be set high. if an error condition in the c channel is detected, the ccs_err bit will be set high. when operating in sd mode, (sd/hd = high), only the ycs_err bit will be set high when checksum errors are detected. although the GS1560A/gs1561 will calculat e and compare checksum values for all ancillary data types by default, the host interface may program the device to check only certain types of ancillary data checksums. this is accomplished via the anc_ type register as described in programmable ancillary data detection on page 49 . ff_line_end_f1 a dd ress: 019h 15-10 ? not use d .?? 9-0 ff_line_end_f1[9:0] fiel d 1 full fiel d en d line d ata use d to set edh c al c ulation ran g e outsi d e of s mpte rp 165 values. r/w 0 table 4-13: host interface description for edh calculation range registers (continued) register name bit name description r/w default
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 60 of 79 4.10.5.5 line based crc error detection the GS1560A/gs1561 will calculate line based crc words for hd vide o signals for both the y and c data channels. these calculated crc values are compared with the received crc values and any mismatch is flagged in the ycrc_err and/or ccrc_err bits of the error_status register. line based crc error flags will only be gene rated when the device is operating in hd mode, (sd/hd = low). if a crc error is detected in the y channel, the ycrc_err bit in the error status register will be set high. if a crc error is detected in the c channel, the ccrc_err bit in the error status register is set high. y and c crc errors will also be generated if crc values are not received. 4.10.5.6 hd line number error detection when operating in hd mode, the GS1560A/g s1561 will calculate line numbers based on the timing generated by the internal flywheel. these calculated line numbers are compared with the received line numbers for the y channel data and any mismatch is flagged in the lnum_err bit of the error_status. line number errors will also be generated if line number values are not received. 4.10.5.7 trs e rror detection trs errors flags ar e generated by the GS1560A/gs1561 when: 1. the received trs timing does not correspond to the internal flywheel timing; or 2. the received trs hamming codes are incorrect. both 8-bit and 10-bit sav and eav trs words are checked for timing and data integrity errors. these are flagged via the sav_err and/or eav_err bits of the error_status register. timing-based trs errors will only be generated if the fw_en/dis pin is set high. note: in hd mode, (sd/hd = low), only the y channel trs codes will be checked for errors. 4.10.6 error correc tion and insertion in addition to signal er ror detection and indication , the GS1560A/gs1561 may also correct certain types of erro rs by inserting corrected code words, checksums and crc values into the data stream. these features are only available in smpte mode and ioproc_en/ dis must be set high. individual correction features may be enabled or disabled via the ioproc_disable register ( table 4-14 ). all of the ioproc_disable register bits defaul t to '0' after device reset, enabling all of the processing features. to disable any indi vidual error correction feature, the host interface must set the corresponding bit high in the ioproc_disable register.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 61 of 79 4.10.6.1 illegal code remapping if the illegal_remap bit of the ioproc_disable register is set low, the GS1560A will remap all codes within the active picture between the values of 3fch and 3ffh to 3fbh. all codes within the active picture ar ea between the values of 000h and 003h will be re-mapped to 004h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values if this feature is enabled. 4.10.6.2 edh crc error correction the GS1560A/gs1561 will ge nerate and inse rt active picture an d full field crc words into the edh data packets received by the device. this feature is only available in sd mode and is enabled by setting the edh_cr c_ins bit of the ioproc_disable register low. edh crc calculation ranges are described in edh crc error detection on page 57 . note: although the GS1560A/gs1561 will modi fy and insert edh crc words and edh packet checksums, edh error flags will not be updated by the device. table 4-14: host interface description for internal processing disable register register name bit name description r/w default iopro c _di s able a dd ress: 000h 15-9 ? not use d .?? 8h_ c onfi g horizontal syn c timin g output c onfi g uration. s et low for a c tive line b lankin g timin g . s et hi g h for h b lankin g b ase d on the h b it settin g of the tr s wor d s. s ee fi g ure 4-2 . 0 7-6 ? not use d .?? 5ille g al_remap ille g al c o d e re-mappin g . c orre c tion of ille g al c o d e wor d s within the a c tive pi c ture. s et hi g h to d isa b le. the iopro c _en/di s pin must b e set hi g h. r/w 0 4 edh_ c r c _in s error dete c tion & han d lin g (edh) c y c li c al re d un d an c y c he c k ( c r c ) error c orre c tion insertion. in s d mo d e set hi g h to d isa b le. the iopro c _en/di s pin must b e set hi g h. r/w 0 3an c _ cs um_in s an c illary data c he c k-sum insertion. s et hi g h to d isa b le. the iopro c _en/di s pin must b e set hi g h. r/w 0 2 c r c _in s y an d c line b ase d c r c insertion. in hd mo d e, inserts line b ase d c r c wor d s in b oth the y an d c c hannels. s et hi g h to d isa b le. the iopro c _en/di s pin must b e set hi g h. r/w 0 1lnum_in s y an d c line num b er insertion. in hd mo d e set hi g h to d isa b le. the iopro c _en/di s pin must b e set hi g h. r/w 0 0tr s _in s timin g referen c e s i g nal insertion. s et hi g h to d isa b le. the iopro c _en/di s pin must b e set hi g h. r/w 0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 62 of 79 4.10.6.3 ancillary data checksum error correction when ancillary data checksum error corr ection and insertion is enabled, the GS1560A/gs1561 will genera te and insert anci llary data checksum s for all ancillary data words by default. where user specified ancillary data has been programmed into the device, (see programmable ancillary data detection on page 49 ), only the checksums for the programmed ancilla ry data types will be corrected. this feature is enabled when the anc_csum_ins bit of the ioproc_disable register is set low. 4.10.6.4 line based crc correction the GS1560A/gs1561 will generate and insert line based crc words into both the y and c channels of the data stream. this feature is only available in hd mode and is enabled by setting the crc_ins bit of th e ioproc_disable register low. 4.10.6.5 hd line number error correction in hd mode, the GS1560A/gs1561 will calculate and insert line numbers into the y and c channels of the output data stream. line number generation is in accordance with the relevant hd video standard as determined by the device, (see automatic video standard and data format detection on page 51 ). this feature is enabled when sd/hd = low, and the lnum_ins bit of the ioproc_disable regi ster is set low. 4.10.6.6 trs error correction when trs error correction and insertion is enabled, the GS1560A/gs1561 will generate and insert 10-bit trs code words as required. trs word generation will be performed in accordance with the timing parameters generated by the flywheel to provide an element of noise immunity. as a result, trs correction will only take place if the flywheel is enabled, (fw_en/dis = high). in addition, the trs_ins bit of the ioproc_disable register must be set low. 4.10.7 edh flag detection as described in edh crc error detection on page 57 , the GS1560A/gs1561 can detect edh packets in the received data stream. the edh flags for ancillary data, active picture and full field areas are extracted from the detected edh packets and placed in the edh_flag register of the device ( table 4-15 ). one set of flags is provided for both fields 1 and 2. field 1 flag data will be overwritten by field 2 flag data. the edh_flag register may be read by the host interface at any time during the received frame except on the lines defi ned in smpte rp165 where these flags are updated.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 63 of 79 note 1: by programming the anc_type1 re gister (005h) with the did word for edh ancillary packets, the application layer may detect a high-to-low transition on either the yanc or canc output pin of the GS1560A/gs1561 to dete rmine (a) when edh packets have been received by the device, and (b) wh en the edh_flag register can be read by the host interface. see ancillary data detection and indication on page 47 for more information on ancillary data detection and indication. note 2: the bits of the edh_flag register are sticky and will not be cleared by a read operation. if the gs 1560a/gs1561 is decoding a source containing edh packets, where edh flags may be set, and the source is replaced by one without edh packets, the edh_flag register will not be cleared. note 3: the GS1560A/gs1561 will detect edh fl ags, but will not update the flags if an edh crc error is detected. ge nnum's gs1532 multi-rate serial izer allows the host to individually set edh flags. table 4-15: host interface description for edh flag register register name bit name description r/w default edh_fla g a dd ress: 003h 15 ? not use d .?? 14 an c -ue s out an c illary unknown error s tatus fla g .r0 13 an c -ida out an c illary internal d evi c e error dete c te d alrea d y fla g .r0 12 an c -idh out an c illary internal d evi c e error dete c te d here fla g .r0 11 an c -eda out an c illary error dete c te d alrea d y fla g .r0 10 an c -edh out an c illary error dete c te d here fla g .r0 9ff-ue s out full fiel d unknown error s tatus fla g .r0 8 ff-ida out full fiel d internal d evi c e error dete c te d alrea d y fla g .r0 7 ff-idh out full fiel d internal d evi c e error dete c te d here fla g .r0 6 ff-eda out full fiel d error dete c te d alrea d y fla g .r0 5 ff-edh out full fiel d error dete c te d here fla g .r0 4ap-ue s out a c tive pi c ture unknown error s tatus fla g .r0 3ap-ida out a c tive pi c ture internal d evi c e error dete c te d alrea d y fla g . r0 2ap-idh out a c tive pi c ture internal d evi c e error dete c te d here fla g .r 0 1 ap-eda out a c tive pi c ture error dete c te d alrea d y fla g .r0 0 ap-edh out a c tive pi c ture error dete c te d here fla g .r0
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 64 of 79 4.11 parallel data outputs data outputs leave the device on the rising edge of pclk as shown in figure 4-7 and figure 4-8 . the data may be scrambled or unscrambled, framed or unframed, and may be presented in 10-bit or 20-bit format. the output data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin. likewise, the output data format is defined by the setting of the external sd/hd , smpte_bypass and dvb_asi pins. recall that in slave mode, these pins are set by the application layer as inputs to the device. in master mode, however, the GS1560A sets the sd/hd and smpte_bypass pins as output status signals. 4.11.1 parallel data bus buffers the parallel data outputs of the GS1560A/gs 1561 are driven by hi gh-impedance buffers which support both lvttl and lvcmos levels. these buffers use a separate power supply of +3.3v dc supplied via the io_vdd and io_gnd pins. all output buffers, including the pclk output, may be driven to a high-impedance state if the reset_trst signal is asserted low. note that the timing characteristics of the parallel data output buffers are optimized for 10-bit hd operation. as shown in figure 4-7 , the output data hold time for hd is 1.5ns. due to this optimization, however, the output data hold time for sd data is so small that the rising edge of the pclk is nearly incident with the data transition. to improve output hold time at sd rates, the pclk ou tput is inverted is sd mode, (sd/hd = high). this is shown in figure 4-8 . fi g ure 4-7: hd p c lk to data timin g pclk dout[19:0] data control signal output t oh t od hd mode
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 65 of 79 fi g ure 4-8: s d p c lk to data timin g 4.11.2 parallel output in smpte mode when the device is operating in smpte mode, (see smpte functionality on page 36 ), both sd and hd data may be presented to the output bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. in 20-bit mode, (20bit/10bit = high), the output data will be word aligned, demultiplexed luma and chroma data. luma words will alwa ys appear on dout[19:10] while chroma words wi ll occupy dout[9:0]. in 10-bit mode, (20bit/10bit = low), the output data will be word aligned, multiplexed luma and chroma data. the da ta will be presented on dout[19:10], and the device will force dout[9:0] low. 4.11.3 parallel output in dvb-asi mode when operating in dvb-asi mode, (see dvb-asi functionality on page 44 ), the GS1560A/gs1561 automatically configures th e output port for 10-bit operation regardless of the setting of the 20bit/10bit pin. the extracted 8-bit data words will be presented on dout[17:10] such that dout17 = hout is the most significant bit of the decoded transport stream data and dout10 = aout is the least significant bit. in addition, dout19 an d dout18 will be configured as the dvb-asi status signals syncout and worderr respectively. see status signal outputs on page 45 for a description of these dvb-asi specific output signals. dout[9:0] will be forced low when the GS1560A/gs1561 is operating in dvb-asi mode. 4.11.4 parallel output in data-through mode when operating in data-through mode, (see data through mode on page 45 ), the GS1560A/gs1561 presents data to the outp ut data bus withou t performing any decoding, descrambling or word-alignment. pclk dout[19:0] data control signal output t oh t od sd mode
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 66 of 79 as described in data through mode on page 45 , the data bus outputs will be forced to logic low if the device is set to operate in master mode but cannot identify smpte trs id words in the input data stream. 4.11.5 parallel output clock (pclk) the frequency of the pclk output signal of the GS1560A/gs1561 is determined by the output data format. table 4-16 below lists the possible outp ut signal formats and their corresponding parallel clock rates. note that dvb-asi output will always be in 10-bit format, regardless of the setting of the 20bit/10bit pin. table 4-16: parallel data output format output data format dout [19:10] dout [9:0] pclk status / control signals* 20bit/ 10bit sd/hd smpte_bypass dvb_asi smpte mode 20 b it demultiplexed s dluma c hroma 13.5mhz hi g hhi g hhi g hlow 10 b it multiplexed s d luma / c hroma for c ed low 27mhz low hi g hhi g hlow 20 b it demultiplexed hd luma c hroma 74.25 or 74.25/ 1.001mhz hi g hlowhi g hlow 10 b it multiplexed hd luma / c hroma for c ed low 148.5 or 148.5/ 1.001mhz low low hi g hlow dvb-asi mode 10 b it dvb-a s idvb-a s i data for c ed low 27mhz hi g hhi g hlow hi g h dvb-a s i data for c ed low 27mhz low hi g hlow hi g h data-through mode** 20 b it demultiplexed s d data data 13.5mhz hi g hhi g hlow low 10 b it multiplexed s ddata for c ed low 27mhz low hi g hlow low 20 b it demultiplexed hd data data 74.25 or 74.25/ 1.001mhz hi g h low low low 10 b it multiplexed hd data for c ed low 148.5 or 148.5/ 1.001mhz low low low low *note1: re c all that s d/hd , s mpte_bypa ss , an d dvb_a s i are input c ontrol pins in slave mo d e to b e set b y the appli c ation layer, b ut the s d/hd an d s mpte_bypa ss pins are output status si g nals set b y the d evi c e in master mo d e. **note 2: data-throu g h mo d e is only availa b le in slave mo d e data throu g h mo d e on pa g e 45 .
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 67 of 79 4.12 gspi host interface the gspi, or gennum serial peripheral interfac e, is a 4-wire interface provided to allow the host to enable additional features of th e device and /or to provide additional status information through configuratio n registers in the GS1560A/gs1561. the gspi comprises a serial data input signal sdin, serial data output signal sdout, an active low ch ip select cs , and a burst clock sclk. the burst clock must have a duty cycle between 40% and 60%. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the host interface. the sdout pin is a high-impedance output allowing multiple devices to be connected in parallel an d selected via the cs input. the interface is illustrated in figure 4-9 . all read or write acce ss to the GS1560A/gs1561 is initia ted and terminated by the host processor. each access always begins with a 16-bit comman d word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. fi g ure 4-9: g ennum s erial peripheral interfa c e ( gs pi) 4.12.1 command word description the command word is transmitted msb first and contains a read/write bit, nine reserved bits and a 6-bit register address. set r/w = '1' to read and r/w = '0' to write from the gspi. command words are clocked in to the GS1560A/gs1561 on the ri sing edge of the serial clock sclk. the appropriate chip select, cs , signal must be asserted low a minimum of 1.5ns (t 0 in figure 4-12 and figure 4-13 ) before the first clock edge to ensure proper operation. each command word must be followed by only one data word to ensure proper operation. fi g ure 4-10: c omman d wor d sclk cs sdout sdin sclk cs sdin sdout application host gs15 6 0a / gs15 6 1 r/w rsv rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv msb lsb
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 68 of 79 fi g ure 4-11: data wor d 4.12.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 4-12 and figure 4-13 respectively. the maximum sclk frequency allowed is 6.6mhz. when writing to the registers via the gspi, the msb of the data word may be presented to sdin immediately following the falling edge of the lsb of the command word. all sdin data is sampled on the rising edge of sclk. when reading from the registers via the gspi, the msb of the data word will be available on sdout 12ns following the falling edge of the lsb of the command word, and thus may be read by the host on the very next rising edge of the clock. the remaining bits are clocked out by the GS1560A on the negative edges of sclk. fi g ure 4-12: gs pi rea d mo d e timin g fi g ure 4-13: gs pi write mo d e timin g 4.12.3 configuration and status registers table 4-17 summarizes the GS1560A /gs1561's internal status and configuration registers. all of these registers are available to the host via the gspi and are all individually addressable. where status registers contain less than the full 16 bits of information however, two or more registers may be combined at a single logical address. d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 msb lsb sdout r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period t 5 t 6 output data hold time r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 69 of 79 4.13 jtag when the jtag/host input pin of the GS1560A/gs1561 is set high, the host interface port will be configured for jtag test operation. in this mode, pins 27 through 30 become tms, tdo, tdi, and tck. in addition, the reset_trst pin will operate as the test reset pin. boundary scan testing usin g the jtag interface will be enabled in this mode. there are two methods in which jtag can be used on the GS1560A/gs1561: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applicatio ns such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with tri-state buffers used in conjunction with the jtag/host input signal. this is shown in figure 4-14 . fi g ure 4-14: in- c ir c uit j ta g table 4-17: GS1560A internal registers address register name see section 000h iopro c _di s able s e c tion 4.10.6 001h error_ s tatu s s e c tion 4.10.5 003h edh_fla g s e c tion 4.10.7 004h video_ s tandard s e c tion 4.10.4 005h - 009h an c _type s e c tion 4.10.2.1 00 c h - 00dh video_format s e c tion 4.10.3 00eh - 011h ra s ter_ s tru c ture s e c tion 4.10.4 012h - 019h edh_ c al c _ran g e s s e c tion 4.10.5.2 01ah error_ma s k s e c tion 4.10.5 application host gs15 6 0a / gs15 6 1 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 70 of 79 alternatively, if the test capabilities are to be used in the system, the host may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 4-15 . fi g ure 4-15: s ystem j ta g please contact your gennum representative to obtain the bsdl model for the GS1560A/gs1561. 4.14 device power up the GS1560A/gs1561 has a recomm ended power supply sequen ce. to ensure correct power up, power the core_vdd pins before the io_vdd pins. device pins may also be driven prior to power up without causing damage. to ensure that all internal registers are cleared upon power-up, the application layer must hold the reset_trst signal low for a minimum of 1ms after the core power supply has reached the minimum level specified in table 2-1 . see figure 4-16 . 4.15 device reset in order to initialize all internal operating conditions to their default states the application layer must hold the reset_trst signal low for a minimum of t reset = 1ms. when held in reset, all device outputs will be driven to a high-impedance state. fi g ure 4-16: reset pulse application host gs15 6 0a / gs15 6 1 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe tri-state c ore_vdd re s et_tr s t t reset +1.65v +1.8v reset reset t reset
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 71 of 79 5. application reference design 5.1 GS1560A typical app lication circuit (part a) eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc gs1524 14 15 1 2 3 4 7 5 6 1 6 9 10 11 13 8 12 vee vcc cli vcca veea sdi rsvd sdi veea mute/cd bypass mcladj vee sdo rsvd sdo 2n4400 1 3 2 0 2n4402 1 2 3 37r4 10k 0 gs1524 14 15 1 2 3 4 7 5 6 1 6 9 10 11 13 8 12 vee vcc cli vcca veea sdi rsvd sdi veea mute/cd bypass mcladj vee sdo rsvd sdo 1u header 1 2 3 10n 75 6 .4n 2n4402 1 2 3 1k 75 2k2 pot 2n4400 1 3 2 10k 75 6 .4n 37r4 pot 1u 0 10n 1u 0 1u 1k 10n header 1 2 3 10n 2k2 75 ddi2 ddi2b sdi cd2b cd1b sdi ddi1b ddi1 1u 1u gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 72 of 79 5.2 GS1560A typical app lication circuit (part b) lock yanc canc ipsel sd/hdb 20bit/10bitb ioproc_en/disb data0 data7 data12 data1 data8 data13 data14 data1 6 data3 data 6 data2 data11 data4 data17 data10 data15 data18 data9 data5 master/slaveb rc_bypb fw_en/ disb sdo_en/disb jtag/hostb data19 master/slaveb ioproc_en/disb 20bit/10bitb data_errorb yanc canc +1.8v +3.3v +1.8v_a +1.8v +3.3v +3.3v vco_vcc +1.8v_a +1.8v_a +3.3v vco_vcc vco_vcc +1.8v_a gs15 6 0a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 24 25 2 6 27 28 29 30 31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 47 48 49 50 51 52 53 55 54 5 6 57 58 59 6 0 6 1 6 2 6 3 6 4 6 5 66 6 7 6 8 6 9 70 71 72 73 74 75 7 6 77 78 79 80 cp_vdd pdbuff_gnd pd_vdd buff_vdd cd1 ddi_1 term1 ddi_1 dvb_asi ipsel sd/hd 20bit/10bit ioproc_en/dis cd2 ddi_2 term2 ddi_2 smpte_bypass rset cd_vdd sdo_en/dis cd_gnd sdo sdo reset_trst jtag/host cs_tms sdout_tdo sdin_tdi sclk_tck data_error fifo_ld core_gnd f v h core_vdd dout0 dout1 io_gnd io_vdd dout2 dout3 dout4 dout5 dout 6 dout7 dout8 io_gnd dout9 dout10 dout11 io_vdd dout13 dout12 dout14 dout15 dout1 6 dout17 io_gnd io_vdd dout18 dout19 core_vdd yanc canc fw_en/dis core_gnd pclk rc_byp master/slave locked vco vco vco_gnd vco_vcc lf cp_cap lb_cont cp_gnd 75 go1555 (go1525) 5 4 8 2 7 1 3 6 vctr gnd gnd gnd vcc o/p nc gnd 10n l 75 281 +/-1 % 1u 1u c 0 bnc 10n 10n r l 2k2 10n r c 2k2 100n 2k2 10n 10n bnc 10n 4u7 10n 10n 0 39k2 1u 4u7 4k75 +/- 1 % 10n 2k2 1u 4u7 2n2 1u 10n 10n 75 10n 4k75 +/- 1 % 0 10n 10n 1u 10n f v h pclk data[19..0] ddi1 ddi1b ddi2b ddi2 cd1b cd2b dvb_asi sd/hdb reset_trstb data_errorb lock canc fifo_ldb yanc smpte_bypassb sclk_tck sdout_tdo sdin_tdi csb_tms master/slaveb rc_bypb jtag/hostb ipsel fw_en/disb sdo_en/disb 20bit/10bitb ioproc_en/disb note: to guarantee -15db output return loss at hd rates, it is recommended that the gs1528 multi-rate cable driver be used. r, l, c form the output return loss compensation network. values are subject to change. note: smpte_bypassb, sd/hdb, dvb_asi, and rc_bypb are inputs in slave mode (master/slaveb = low), and are outputs in master mode (master/slaveb = high). jtag/hostb ipsel fw_en/disb sdo_en/disb smpte_bypassb sd/hdb dvb_asi rc_bypb pclk data_errorb fifo_ldb lock fifo_ldb dvb_asi smpte_bypassb gnd_eq gnd_eq gnd_a gnd_a gnd_a gnd_a gnd_a gnd_d gnd_d gnd_d gnd_d gnd_a gnd_d gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco 4u7 4u7 4u7 gnd_vco
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 73 of 79 5.3 gs1561 typical application circuit (part a) eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc gs1524 14 15 1 2 3 4 7 5 6 1 6 9 10 11 13 8 12 vee vcc cli vcca veea sdi rsvd sdi veea mute/cd bypass mcladj vee sdo rsvd sdo 2n4400 1 3 2 0 2n4402 1 2 3 37r4 10k 0 gs1524 14 15 1 2 3 4 7 5 6 1 6 9 10 11 13 8 12 vee vcc cli vcca veea sdi rsvd sdi veea mute/cd bypass mcladj vee sdo rsvd sdo 1u header 1 2 3 10n 75 6 .4n 2n4402 1 2 3 1k 75 2k2 pot 2n4400 1 3 2 10k 75 6 .4n 37r4 pot 1u 0 10n 1u 0 1u 1k 10n header 1 2 3 10n 2k2 75 ddi2 ddi2b sdi cd2b cd1b sdi ddi1b ddi1 1u 1u gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 74 of 79 5.4 gs1561 typical application circuit (part b) lock yanc canc ipsel sd/hdb 20bit/10bitb ioproc_en/disb data0 data7 data12 data1 data8 data13 data14 data1 6 data3 data 6 data2 data11 data4 data17 data10 data15 data18 data9 data5 master/slaveb fw_en/ disb jtag/hostb data19 master/slaveb ioproc_en/disb 20bit/10bitb data_errorb yanc canc +1.8v +3.3v +1.8v +3.3v +3.3v vco_vcc +1.8v_a +3.3v vco_vcc vco_vcc gs15 6 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 24 25 2 6 27 28 29 30 31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 47 48 49 50 51 52 53 55 54 5 6 57 58 59 6 0 6 1 6 2 6 3 6 4 6 5 66 6 7 6 8 6 9 70 71 72 73 74 75 7 6 77 78 79 80 cp_vdd pdbuff_gnd pd_vdd buff_vdd cd1 ddi_1 term1 ddi_1 dvb_asi ipsel sd/hd 20bit/10bit ioproc_en/dis cd2 ddi_2 term2 ddi_2 smpte_bypass nc nc nc nc nc reset_trst jtag/host cs_tms sdout_tdo sdin_tdi sclk_tck data_error fifo_ld core_gnd f v h core_vdd dout0 dout1 io_gnd io_vdd dout2 dout3 dout4 dout5 dout 6 dout7 dout8 io_gnd dout9 dout10 dout11 io_vdd dout13 dout12 dout14 dout15 dout1 6 dout17 io_gnd io_vdd dout18 dout19 core_vdd yanc canc fw_en/dis core_gnd pclk rsv master/slave locked vco vco vco_gnd vco_vcc lf cp_cap lb_cont cp_gnd go1555 (go1525) 5 4 8 2 7 1 3 6 vctr gnd gnd gnd vcc o/p nc gnd 10n 1u 1u 0 10n 2k2 10n 2k2 100n 2k2 10n 10n 10n 0 39k2 1u 4u7 4k7 10n 1u 2n2 1u 10n 10n 75 10n 4k7 0 10n 10n 1u 10n f v h pclk data[19..0] ddi1 ddi1b ddi2b ddi2 cd1b cd2b dvb_asi sd/hdb reset_trstb data_errorb lock canc fifo_ldb yanc smpte_bypassb sclk_tck sdout_tdo sdin_tdi csb_tms master/slaveb jtag/hostb ipsel fw_en/disb sdo_en/disb 20bit/10bitb ioproc_en/disb note: smpte_bypassb, sd/hdb, and dvb_asi are inputs in slave mode (master/slaveb = low), and are outputs in master mode (master/slaveb = high). jtag/hostb ipsel fw_en/disb sdo_en/disb smpte_bypassb sd/hdb dvb_asi pclk data_errorb fifo_ldb lock fifo_ldb dvb_asi smpte_bypassb gnd_eq gnd_eq gnd_a gnd_d gnd_d gnd_d gnd_d gnd_a gnd_d gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco 4u7 4u7 4u7 nc 2k2 gnd_vco
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 75 of 79 6. references & relevant standards s mpte 125m c omponent vi d eo si g nal 4:2:2 ? b it parallel interfa c e s mpte 260m 1125 / 60 hi g h d efinition pro d u c tion system ? d i g ital representation an d b it parallel interfa c e s mpte 267m bit parallel d i g ital interfa c e ? c omponent vi d eo si g nal 4:2:2 16 x 9 aspe c t ratio s mpte 274m 1920 x 1080 s c annin g analo g an d parallel d i g ital interfa c es for multiple pi c ture rates s mpte 291m an c illary data pa c ket an d s pa c e formattin g s mpte 292m bit- s erial di g ital interfa c e for hi g h-definition television s ystems s mpte 293m 720 x 483 a c tive line at 59.94 hz pro g ressive s c an pro d u c tion ? d i g ital representation s mpte 296m 1280 x 720 s c annin g , analo g an d d i g ital representation an d analo g interfa c e s mpte 352m vi d eo payloa d i d entifi c ation for di g ital television interfa c es s mpte rp165 error dete c tion c he c kwor d s an d s tatus fla g s for use in bit- s erial di g ital interfa c es for television s mpte rp168 definition of verti c al interval s wit c hin g point for s yn c hronous vi d eo s wit c hin g
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 76 of 79 7. package & ordering information 7.1 package dimensions tolerances of form and position symbol min nom max min nom max millimeter inch 80l b e aaa ccc bbb d2 e2 0.22 0.65 bsc 0.026 bsc 12.35 0.20 0.20 0.10 0.008 0.008 0.004 0.486 0.486 12.35 0.30 0.38 0.009 0.012 0.015 notes: diagram shown is representative only. table x is fixed for all pin sizes, and table y is specific to the 80-pin package. table y ddd 0.13 0.005 table x control dimensions are in millimeters. 1. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 2. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 77 of 79 7.2 packaging data 7.3 solder reflow profiles the device is manufactured with matte-sn terminations and is compatible with both standard eutectic and pb-free solder reflow profiles. the recommended standard eutectic reflow profile is shown in figure 7-1 . msl qualification was performed using the maximum pb-free reflow profile shown in figure 7-2 . fi g ure 7-1: s tan d ar d eute c ti c s ol d er reflow profile parameter value pa c ka g e type 14mm x 14mm 80-pin lqfp pa c ka g e drawin g referen c e j ede c m s 026 moisture s ensitivity level 3 j un c tion to c ase thermal resistan c e, j- c 11.6 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 39.9 c /w psi 0.6 c /w p b -free an d roh s c ompliant yes 25c 100c 150c 183c 230c 220c time temperature 6 min. max 120 sec. max 6 0-150 sec. 10-20 sec. 3c/sec max 6 c/sec max
GS1560A/gs1561 hd-linx? ii dual-rate deserializer data sheet 27360 - 12 june 2009 78 of 79 fi g ure 7-2: maximum p b -free s ol d er reflow profile (p b -free pa c ka g e) 7.4 ordering information 25c 150c 200c 217c 2 6 0c 250c time temperature 8 min. max 6 0-180 sec. max 6 0-150 sec. 20-40 sec. 3c/sec max 6 c/sec max part number pb-free and rohs compliant loop-through package temperature range gs 1560a c f no yes 80-pin lqfp 0 c to 70 c gs 1560a c fe3 yes yes 80-pin lqfp 0 c to 70 c gs 1561- c f no no 80-pin lqfp 0 c to 70 c gs 1561- c fe3 yes no 80-pin lqfp 0 c to 70 c
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